Missed files

CMSIS/STM32L4xx/Include/stm32l4xx.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l4xx.h
   * @author  MCD Application Team
-  * @version V1.3.2
-  * @date    16-June-2017
   * @brief   CMSIS STM32L4xx Device Peripheral Access Layer Header File.
   *
   *          The file is the unique include file that the application programmer
@@ -18,29 +16,13 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under Apache License, Version 2.0,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/Apache-2.0
   *
   ******************************************************************************
   */
@@ -75,10 +57,15 @@
    application
   */
 
-#if !defined (STM32L431xx) && !defined (STM32L432xx) && !defined (STM32L433xx) && !defined (STM32L442xx) && !defined (STM32L443xx) && \
+#if !defined (STM32L412xx) && !defined (STM32L422xx) && \
+    !defined (STM32L431xx) && !defined (STM32L432xx) && !defined (STM32L433xx) && !defined (STM32L442xx) && !defined (STM32L443xx) && \
     !defined (STM32L451xx) && !defined (STM32L452xx) && !defined (STM32L462xx) && \
     !defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx) && \
-    !defined (STM32L496xx) && !defined (STM32L4A6xx)
+    !defined (STM32L496xx) && !defined (STM32L4A6xx) && \
+    !defined (STM32L4P5xx) && !defined (STM32L4Q5xx) && \
+    !defined (STM32L4R5xx) && !defined (STM32L4R7xx) && !defined (STM32L4R9xx) && !defined (STM32L4S5xx) && !defined (STM32L4S7xx) && !defined (STM32L4S9xx)
+  /* #define STM32L412xx */   /*!< STM32L412xx Devices */
+  /* #define STM32L422xx */   /*!< STM32L422xx Devices */
   /* #define STM32L431xx */   /*!< STM32L431xx Devices */
   /* #define STM32L432xx */   /*!< STM32L432xx Devices */
   /* #define STM32L433xx */   /*!< STM32L433xx Devices */
@@ -94,6 +81,13 @@
   /* #define STM32L486xx */   /*!< STM32L486xx Devices */
   /* #define STM32L496xx */   /*!< STM32L496xx Devices */
   /* #define STM32L4A6xx */   /*!< STM32L4A6xx Devices */
+  /* #define STM32L4P5xx */   /*!< STM32L4Q5xx Devices */
+  /* #define STM32L4R5xx */   /*!< STM32L4R5xx Devices */
+  /* #define STM32L4R7xx */   /*!< STM32L4R7xx Devices */
+  /* #define STM32L4R9xx */   /*!< STM32L4R9xx Devices */
+  /* #define STM32L4S5xx */   /*!< STM32L4S5xx Devices */
+  /* #define STM32L4S7xx */   /*!< STM32L4S7xx Devices */
+  /* #define STM32L4S9xx */   /*!< STM32L4S9xx Devices */
 #endif
 
 /*  Tip: To avoid modifying this file each time you need to switch between these
@@ -109,11 +103,11 @@
 #endif /* USE_HAL_DRIVER */
 
 /**
-  * @brief CMSIS Device version number V1.3.2
+  * @brief CMSIS Device version number
   */
 #define __STM32L4_CMSIS_VERSION_MAIN   (0x01) /*!< [31:24] main version */
-#define __STM32L4_CMSIS_VERSION_SUB1   (0x03) /*!< [23:16] sub1 version */
-#define __STM32L4_CMSIS_VERSION_SUB2   (0x02) /*!< [15:8]  sub2 version */
+#define __STM32L4_CMSIS_VERSION_SUB1   (0x07) /*!< [23:16] sub1 version */
+#define __STM32L4_CMSIS_VERSION_SUB2   (0x01) /*!< [15:8]  sub2 version */
 #define __STM32L4_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
 #define __STM32L4_CMSIS_VERSION        ((__STM32L4_CMSIS_VERSION_MAIN << 24)\
                                        |(__STM32L4_CMSIS_VERSION_SUB1 << 16)\
@@ -128,7 +122,11 @@
   * @{
   */
 
-#if defined(STM32L431xx)
+#if defined(STM32L412xx)
+  #include "stm32l412xx.h"
+#elif defined(STM32L422xx)
+  #include "stm32l422xx.h"
+#elif defined(STM32L431xx)
   #include "stm32l431xx.h"
 #elif defined(STM32L432xx)
   #include "stm32l432xx.h"
@@ -158,6 +156,22 @@
   #include "stm32l496xx.h"
 #elif defined(STM32L4A6xx)
   #include "stm32l4a6xx.h"
+#elif defined(STM32L4P5xx)
+  #include "stm32l4p5xx.h"
+#elif defined(STM32L4Q5xx)
+  #include "stm32l4q5xx.h"
+#elif defined(STM32L4R5xx)
+  #include "stm32l4r5xx.h"
+#elif defined(STM32L4R7xx)
+  #include "stm32l4r7xx.h"
+#elif defined(STM32L4R9xx)
+  #include "stm32l4r9xx.h"
+#elif defined(STM32L4S5xx)
+  #include "stm32l4s5xx.h"
+#elif defined(STM32L4S7xx)
+  #include "stm32l4s7xx.h"
+#elif defined(STM32L4S9xx)
+  #include "stm32l4s9xx.h"
 #else
  #error "Please select first the target STM32L4xx device used in your application (in stm32l4xx.h file)"
 #endif
@@ -184,8 +198,8 @@ typedef enum
 
 typedef enum
 {
-  ERROR = 0,
-  SUCCESS = !ERROR
+  SUCCESS = 0,
+  ERROR = !SUCCESS
 } ErrorStatus;
 
 /**

CMSIS/STM32L4xx/Include/system_stm32l4xx.h

@@ -2,35 +2,17 @@
   ******************************************************************************
   * @file    system_stm32l4xx.h
   * @author  MCD Application Team
-  * @version V1.3.2
-  * @date    16-June-2017
   * @brief   CMSIS Cortex-M4 Device System Source File for STM32L4xx devices.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under Apache License, Version 2.0,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/Apache-2.0
   *
   ******************************************************************************
   */

CMSIS/STM32L4xx/Source/Templates/arm/startup_stm32l412xx.s

@@ -0,0 +1,373 @@
+;*******************************************************************************
+;* File Name          : startup_stm32l412xx.s
+;* Author             : MCD Application Team
+;* Description        : STM32L412xx Ultra Low Power devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;*
+;* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
+;*
+;*******************************************************************************
+;* <<< Use Configuration Wizard in Context Menu >>>
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x400;
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x200;
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog
+                DCD     PVD_PVM_IRQHandler                ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+                DCD     FLASH_IRQHandler                  ; FLASH
+                DCD     RCC_IRQHandler                    ; RCC
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4
+                DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7
+                DCD     ADC1_2_IRQHandler                 ; ADC1&2
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+                DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15
+                DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16
+                DCD     TIM1_TRG_COM_IRQHandler           ; TIM1 Trigger and Commutation
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler                   ; TIM2
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+                DCD     SPI1_IRQHandler                   ; SPI1
+                DCD     SPI2_IRQHandler                   ; SPI2
+                DCD     USART1_IRQHandler                 ; USART1
+                DCD     USART2_IRQHandler                 ; USART2
+                DCD     USART3_IRQHandler                 ; USART3
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     TIM6_IRQHandler                   ; TIM6
+                DCD     0                                 ; Reserved
+                DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1
+                DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2
+                DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3
+                DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4
+                DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     COMP_IRQHandler                   ; COMP Interrupt
+                DCD     LPTIM1_IRQHandler                 ; LP TIM1 interrupt
+                DCD     LPTIM2_IRQHandler                 ; LP TIM2 interrupt
+                DCD     USB_IRQHandler                    ; USB FS
+                DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6
+                DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7
+                DCD     LPUART1_IRQHandler                ; LP UART1 interrupt
+                DCD     QUADSPI_IRQHandler                ; Quad SPI global interrupt
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     TSC_IRQHandler                    ; Touch Sense Controller global interrupt
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     RNG_IRQHandler                    ; RNG global interrupt
+                DCD     FPU_IRQHandler                    ; FPU
+                DCD     CRS_IRQHandler                    ; CRS interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+        EXPORT     WWDG_IRQHandler                   [WEAK]
+        EXPORT     PVD_PVM_IRQHandler                [WEAK]
+        EXPORT     TAMP_STAMP_IRQHandler             [WEAK]
+        EXPORT     RTC_WKUP_IRQHandler               [WEAK]
+        EXPORT     FLASH_IRQHandler                  [WEAK]
+        EXPORT     RCC_IRQHandler                    [WEAK]
+        EXPORT     EXTI0_IRQHandler                  [WEAK]
+        EXPORT     EXTI1_IRQHandler                  [WEAK]
+        EXPORT     EXTI2_IRQHandler                  [WEAK]
+        EXPORT     EXTI3_IRQHandler                  [WEAK]
+        EXPORT     EXTI4_IRQHandler                  [WEAK]
+        EXPORT     DMA1_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel5_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel7_IRQHandler          [WEAK]
+        EXPORT     ADC1_2_IRQHandler                 [WEAK]
+        EXPORT     EXTI9_5_IRQHandler                [WEAK]
+        EXPORT     TIM1_BRK_TIM15_IRQHandler         [WEAK]
+        EXPORT     TIM1_UP_TIM16_IRQHandler          [WEAK]
+        EXPORT     TIM1_TRG_COM_IRQHandler           [WEAK]
+        EXPORT     TIM1_CC_IRQHandler                [WEAK]
+        EXPORT     TIM2_IRQHandler                   [WEAK]
+        EXPORT     I2C1_EV_IRQHandler                [WEAK]
+        EXPORT     I2C1_ER_IRQHandler                [WEAK]
+        EXPORT     I2C2_EV_IRQHandler                [WEAK]
+        EXPORT     I2C2_ER_IRQHandler                [WEAK]
+        EXPORT     SPI1_IRQHandler                   [WEAK]
+        EXPORT     SPI2_IRQHandler                   [WEAK]
+        EXPORT     USART1_IRQHandler                 [WEAK]
+        EXPORT     USART2_IRQHandler                 [WEAK]
+        EXPORT     USART3_IRQHandler                 [WEAK]
+        EXPORT     EXTI15_10_IRQHandler              [WEAK]
+        EXPORT     RTC_Alarm_IRQHandler              [WEAK]
+        EXPORT     TIM6_IRQHandler                   [WEAK]
+        EXPORT     DMA2_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel5_IRQHandler          [WEAK]
+        EXPORT     COMP_IRQHandler                   [WEAK]
+        EXPORT     LPTIM1_IRQHandler                 [WEAK]
+        EXPORT     LPTIM2_IRQHandler                 [WEAK]
+        EXPORT     USB_IRQHandler                    [WEAK]
+        EXPORT     DMA2_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel7_IRQHandler          [WEAK]
+        EXPORT     LPUART1_IRQHandler                [WEAK]
+        EXPORT     QUADSPI_IRQHandler                [WEAK]
+        EXPORT     I2C3_EV_IRQHandler                [WEAK]
+        EXPORT     I2C3_ER_IRQHandler                [WEAK]
+        EXPORT     TSC_IRQHandler                    [WEAK]
+        EXPORT     RNG_IRQHandler                    [WEAK]
+        EXPORT     FPU_IRQHandler                    [WEAK]
+        EXPORT     CRS_IRQHandler                    [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM15_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+TIM6_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+COMP_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+USB_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+LPUART1_IRQHandler
+QUADSPI_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+TSC_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+CRS_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

CMSIS/STM32L4xx/Source/Templates/arm/startup_stm32l422xx.s

@@ -0,0 +1,375 @@
+;*******************************************************************************
+;* File Name          : startup_stm32l422xx.s
+;* Author             : MCD Application Team
+;* Description        : STM32L422xx Ultra Low Power devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;*
+;* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
+;*
+;*******************************************************************************
+;* <<< Use Configuration Wizard in Context Menu >>>
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x400;
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x200;
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog
+                DCD     PVD_PVM_IRQHandler                ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+                DCD     FLASH_IRQHandler                  ; FLASH
+                DCD     RCC_IRQHandler                    ; RCC
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4
+                DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7
+                DCD     ADC1_2_IRQHandler                 ; ADC1&2
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+                DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15
+                DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16
+                DCD     TIM1_TRG_COM_IRQHandler           ; TIM1 Trigger and Commutation
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler                   ; TIM2
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+                DCD     SPI1_IRQHandler                   ; SPI1
+                DCD     SPI2_IRQHandler                   ; SPI2
+                DCD     USART1_IRQHandler                 ; USART1
+                DCD     USART2_IRQHandler                 ; USART2
+                DCD     USART3_IRQHandler                 ; USART3
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     TIM6_IRQHandler                   ; TIM6
+                DCD     0                                 ; Reserved
+                DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1
+                DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2
+                DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3
+                DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4
+                DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     COMP_IRQHandler                   ; COMP Interrupt
+                DCD     LPTIM1_IRQHandler                 ; LP TIM1 interrupt
+                DCD     LPTIM2_IRQHandler                 ; LP TIM2 interrupt
+                DCD     USB_IRQHandler                    ; USB FS
+                DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6
+                DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7
+                DCD     LPUART1_IRQHandler                ; LP UART1 interrupt
+                DCD     QUADSPI_IRQHandler                ; Quad SPI global interrupt
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     TSC_IRQHandler                    ; Touch Sense Controller global interrupt
+                DCD     0                                 ; Reserved
+                DCD     AES_IRQHandler                    ; AES global interrupt
+                DCD     RNG_IRQHandler                    ; RNG global interrupt
+                DCD     FPU_IRQHandler                    ; FPU
+                DCD     CRS_IRQHandler                    ; CRS interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+        EXPORT     WWDG_IRQHandler                   [WEAK]
+        EXPORT     PVD_PVM_IRQHandler                [WEAK]
+        EXPORT     TAMP_STAMP_IRQHandler             [WEAK]
+        EXPORT     RTC_WKUP_IRQHandler               [WEAK]
+        EXPORT     FLASH_IRQHandler                  [WEAK]
+        EXPORT     RCC_IRQHandler                    [WEAK]
+        EXPORT     EXTI0_IRQHandler                  [WEAK]
+        EXPORT     EXTI1_IRQHandler                  [WEAK]
+        EXPORT     EXTI2_IRQHandler                  [WEAK]
+        EXPORT     EXTI3_IRQHandler                  [WEAK]
+        EXPORT     EXTI4_IRQHandler                  [WEAK]
+        EXPORT     DMA1_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel5_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel7_IRQHandler          [WEAK]
+        EXPORT     ADC1_2_IRQHandler                 [WEAK]
+        EXPORT     EXTI9_5_IRQHandler                [WEAK]
+        EXPORT     TIM1_BRK_TIM15_IRQHandler         [WEAK]
+        EXPORT     TIM1_UP_TIM16_IRQHandler          [WEAK]
+        EXPORT     TIM1_TRG_COM_IRQHandler           [WEAK]
+        EXPORT     TIM1_CC_IRQHandler                [WEAK]
+        EXPORT     TIM2_IRQHandler                   [WEAK]
+        EXPORT     I2C1_EV_IRQHandler                [WEAK]
+        EXPORT     I2C1_ER_IRQHandler                [WEAK]
+        EXPORT     I2C2_EV_IRQHandler                [WEAK]
+        EXPORT     I2C2_ER_IRQHandler                [WEAK]
+        EXPORT     SPI1_IRQHandler                   [WEAK]
+        EXPORT     SPI2_IRQHandler                   [WEAK]
+        EXPORT     USART1_IRQHandler                 [WEAK]
+        EXPORT     USART2_IRQHandler                 [WEAK]
+        EXPORT     USART3_IRQHandler                 [WEAK]
+        EXPORT     EXTI15_10_IRQHandler              [WEAK]
+        EXPORT     RTC_Alarm_IRQHandler              [WEAK]
+        EXPORT     TIM6_IRQHandler                   [WEAK]
+        EXPORT     DMA2_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel5_IRQHandler          [WEAK]
+        EXPORT     COMP_IRQHandler                   [WEAK]
+        EXPORT     LPTIM1_IRQHandler                 [WEAK]
+        EXPORT     LPTIM2_IRQHandler                 [WEAK]
+        EXPORT     USB_IRQHandler                    [WEAK]
+        EXPORT     DMA2_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel7_IRQHandler          [WEAK]
+        EXPORT     LPUART1_IRQHandler                [WEAK]
+        EXPORT     QUADSPI_IRQHandler                [WEAK]
+        EXPORT     I2C3_EV_IRQHandler                [WEAK]
+        EXPORT     I2C3_ER_IRQHandler                [WEAK]
+        EXPORT     TSC_IRQHandler                    [WEAK]
+        EXPORT     AES_IRQHandler                    [WEAK]
+        EXPORT     RNG_IRQHandler                    [WEAK]
+        EXPORT     FPU_IRQHandler                    [WEAK]
+        EXPORT     CRS_IRQHandler                    [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM15_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+TIM6_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+COMP_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+USB_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+LPUART1_IRQHandler
+QUADSPI_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+TSC_IRQHandler
+AES_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+CRS_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

CMSIS/STM32L4xx/Source/Templates/arm/startup_stm32l431xx.s

@@ -1,8 +1,6 @@
-;********************** COPYRIGHT(c) 2017  STMicroelectronics ******************
+;*******************************************************************************
 ;* File Name          : startup_stm32l431xx.s
 ;* Author             : MCD Application Team
-;* Version            : V1.3.2
-;* Date               : 16-June-2017
 ;* Description        : STM32L431xx Ultra Low Power devices vector table for MDK-ARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -12,33 +10,18 @@
 ;*                        calls main()).
 ;*                      After Reset the Cortex-M4 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;*
+;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
+;*
+;*******************************************************************************
 ;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
-;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
-;*******************************************************************************
-;
 ; Amount of memory (in bytes) allocated for Stack
 ; Tailor this value to your application needs
 ; <h> Stack Configuration

CMSIS/STM32L4xx/Source/Templates/arm/startup_stm32l432xx.s

@@ -1,8 +1,6 @@
-;********************** COPYRIGHT(c) 2017  STMicroelectronics ******************
+;*******************************************************************************
 ;* File Name          : startup_stm32l432xx.s
 ;* Author             : MCD Application Team
-;* Version            : V1.3.2
-;* Date               : 16-June-2017
 ;* Description        : STM32L432xx Ultra Low Power devices vector table for MDK-ARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -12,33 +10,18 @@
 ;*                        calls main()).
 ;*                      After Reset the Cortex-M4 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;*
+;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
+;*
+;*******************************************************************************
 ;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
-;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
-;*******************************************************************************
-;
 ; Amount of memory (in bytes) allocated for Stack
 ; Tailor this value to your application needs
 ; <h> Stack Configuration

CMSIS/STM32L4xx/Source/Templates/arm/startup_stm32l433xx.s

@@ -1,8 +1,6 @@
-;********************** COPYRIGHT(c) 2017  STMicroelectronics ******************
+;*******************************************************************************
 ;* File Name          : startup_stm32l433xx.s
 ;* Author             : MCD Application Team
-;* Version            : V1.3.2
-;* Date               : 16-June-2017
 ;* Description        : STM32L433xx Ultra Low Power devices vector table for MDK-ARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -12,33 +10,18 @@
 ;*                        calls main()).
 ;*                      After Reset the Cortex-M4 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;*
+;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
+;*
+;*******************************************************************************
 ;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
-;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
-;*******************************************************************************
-;
 ; Amount of memory (in bytes) allocated for Stack
 ; Tailor this value to your application needs
 ; <h> Stack Configuration

CMSIS/STM32L4xx/Source/Templates/arm/startup_stm32l442xx.s

@@ -1,8 +1,6 @@
-;********************** COPYRIGHT(c) 2017  STMicroelectronics ******************
+;*******************************************************************************
 ;* File Name          : startup_stm32l442xx.s
 ;* Author             : MCD Application Team
-;* Version            : V1.3.2
-;* Date               : 16-June-2017
 ;* Description        : STM32L442xx Ultra Low Power devices vector table for MDK-ARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -12,33 +10,18 @@
 ;*                        calls main()).
 ;*                      After Reset the Cortex-M4 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;*
+;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
+;*
+;*******************************************************************************
 ;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
-;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
-;*******************************************************************************
-;
 ; Amount of memory (in bytes) allocated for Stack
 ; Tailor this value to your application needs
 ; <h> Stack Configuration

CMSIS/STM32L4xx/Source/Templates/arm/startup_stm32l443xx.s

@@ -1,8 +1,6 @@
-;********************** COPYRIGHT(c) 2017  STMicroelectronics ******************
+;*******************************************************************************
 ;* File Name          : startup_stm32l443xx.s
 ;* Author             : MCD Application Team
-;* Version            : V1.3.2
-;* Date               : 16-June-2017
 ;* Description        : STM32L443xx Ultra Low Power devices vector table for MDK-ARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -12,33 +10,18 @@
 ;*                        calls main()).
 ;*                      After Reset the Cortex-M4 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;*
+;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
+;*
+;*******************************************************************************
 ;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
-;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
-;*******************************************************************************
-;
 ; Amount of memory (in bytes) allocated for Stack
 ; Tailor this value to your application needs
 ; <h> Stack Configuration

CMSIS/STM32L4xx/Source/Templates/arm/startup_stm32l451xx.s

@@ -1,8 +1,6 @@
-;********************** COPYRIGHT(c) 2017  STMicroelectronics ******************
+;*******************************************************************************
 ;* File Name          : startup_stm32l451xx.s
 ;* Author             : MCD Application Team
-;* Version            : V1.3.2
-;* Date               : 16-June-2017
 ;* Description        : STM32L451xx Ultra Low Power devices vector table for MDK-ARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -12,33 +10,18 @@
 ;*                        calls main()).
 ;*                      After Reset the Cortex-M4 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;*
+;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
+;*
+;*******************************************************************************
 ;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
-;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
-;*******************************************************************************
-;
 ; Amount of memory (in bytes) allocated for Stack
 ; Tailor this value to your application needs
 ; <h> Stack Configuration

CMSIS/STM32L4xx/Source/Templates/arm/startup_stm32l452xx.s

@@ -1,8 +1,6 @@
-;********************** COPYRIGHT(c) 2017  STMicroelectronics ******************
+;*******************************************************************************
 ;* File Name          : startup_stm32l452xx.s
 ;* Author             : MCD Application Team
-;* Version            : V1.3.2
-;* Date               : 16-June-2017
 ;* Description        : STM32L452xx Ultra Low Power devices vector table for MDK-ARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -12,33 +10,18 @@
 ;*                        calls main()).
 ;*                      After Reset the Cortex-M4 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;*
+;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
+;*
+;*******************************************************************************
 ;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
-;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
-;*******************************************************************************
-;
 ; Amount of memory (in bytes) allocated for Stack
 ; Tailor this value to your application needs
 ; <h> Stack Configuration

CMSIS/STM32L4xx/Source/Templates/arm/startup_stm32l462xx.s

@@ -1,8 +1,6 @@
-;********************** COPYRIGHT(c) 2017  STMicroelectronics ******************
+;*******************************************************************************
 ;* File Name          : startup_stm32l462xx.s
 ;* Author             : MCD Application Team
-;* Version            : V1.3.2
-;* Date               : 16-June-2017
 ;* Description        : STM32L462xx Ultra Low Power devices vector table for MDK-ARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -12,33 +10,18 @@
 ;*                        calls main()).
 ;*                      After Reset the Cortex-M4 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;*
+;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
+;*
+;*******************************************************************************
 ;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
-;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
-;*******************************************************************************
-;
 ; Amount of memory (in bytes) allocated for Stack
 ; Tailor this value to your application needs
 ; <h> Stack Configuration

CMSIS/STM32L4xx/Source/Templates/arm/startup_stm32l471xx.s

@@ -1,8 +1,6 @@
-;********************** COPYRIGHT(c) 2017  STMicroelectronics ******************
+;*******************************************************************************
 ;* File Name          : startup_stm32l471xx.s
 ;* Author             : MCD Application Team
-;* Version            : V1.3.2
-;* Date               : 16-June-2017
 ;* Description        : STM32L471xx Ultra Low Power devices vector table for MDK-ARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -12,33 +10,18 @@
 ;*                        calls main()).
 ;*                      After Reset the Cortex-M4 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;*
+;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
+;*
+;*******************************************************************************
 ;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
-;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
-;*******************************************************************************
-;
 ; Amount of memory (in bytes) allocated for Stack
 ; Tailor this value to your application needs
 ; <h> Stack Configuration

CMSIS/STM32L4xx/Source/Templates/arm/startup_stm32l475xx.s

@@ -1,8 +1,6 @@
-;********************** COPYRIGHT(c) 2017  STMicroelectronics ******************
+;*******************************************************************************
 ;* File Name          : startup_stm32l475xx.s
 ;* Author             : MCD Application Team
-;* Version            : V1.3.2
-;* Date               : 16-June-2017
 ;* Description        : STM32L475xx Ultra Low Power devices vector table for MDK-ARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -12,33 +10,18 @@
 ;*                        calls main()).
 ;*                      After Reset the Cortex-M4 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;*
+;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
+;*
+;*******************************************************************************
 ;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
-;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
-;*******************************************************************************
-;
 ; Amount of memory (in bytes) allocated for Stack
 ; Tailor this value to your application needs
 ; <h> Stack Configuration

CMSIS/STM32L4xx/Source/Templates/arm/startup_stm32l476xx.s

@@ -1,8 +1,6 @@
-;********************** COPYRIGHT(c) 2017  STMicroelectronics ******************
+;*******************************************************************************
 ;* File Name          : startup_stm32l476xx.s
 ;* Author             : MCD Application Team
-;* Version            : V1.3.2
-;* Date               : 16-June-2017
 ;* Description        : STM32L476xx Ultra Low Power devices vector table for MDK-ARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -12,33 +10,18 @@
 ;*                        calls main()).
 ;*                      After Reset the Cortex-M4 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;*
+;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
+;*
+;*******************************************************************************
 ;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
-;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
-;*******************************************************************************
-;
 ; Amount of memory (in bytes) allocated for Stack
 ; Tailor this value to your application needs
 ; <h> Stack Configuration

CMSIS/STM32L4xx/Source/Templates/arm/startup_stm32l485xx.s

@@ -1,8 +1,6 @@
-;********************** COPYRIGHT(c) 2017  STMicroelectronics ******************
+;*******************************************************************************
 ;* File Name          : startup_stm32l485xx.s
 ;* Author             : MCD Application Team
-;* Version            : V1.3.2
-;* Date               : 16-June-2017
 ;* Description        : STM32L485xx Ultra Low Power devices vector table for MDK-ARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -12,33 +10,18 @@
 ;*                        calls main()).
 ;*                      After Reset the Cortex-M4 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;*
+;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
+;*
+;*******************************************************************************
 ;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
-;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
-;*******************************************************************************
-;
 ; Amount of memory (in bytes) allocated for Stack
 ; Tailor this value to your application needs
 ; <h> Stack Configuration

CMSIS/STM32L4xx/Source/Templates/arm/startup_stm32l486xx.s

@@ -1,8 +1,6 @@
-;********************** COPYRIGHT(c) 2017  STMicroelectronics ******************
+;*******************************************************************************
 ;* File Name          : startup_stm32l486xx.s
 ;* Author             : MCD Application Team
-;* Version            : V1.3.2
-;* Date               : 16-June-2017
 ;* Description        : STM32L486xx Ultra Low Power devices vector table for MDK-ARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -12,33 +10,18 @@
 ;*                        calls main()).
 ;*                      After Reset the Cortex-M4 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;*
+;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
+;*
+;*******************************************************************************
 ;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
-;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
-;*******************************************************************************
-;
 ; Amount of memory (in bytes) allocated for Stack
 ; Tailor this value to your application needs
 ; <h> Stack Configuration

CMSIS/STM32L4xx/Source/Templates/arm/startup_stm32l496xx.s

@@ -1,8 +1,6 @@
-;********************** COPYRIGHT(c) 2017  STMicroelectronics ******************
+;*******************************************************************************
 ;* File Name          : startup_stm32l496xx.s
 ;* Author             : MCD Application Team
-;* Version            : V1.3.2
-;* Date               : 16-June-2017
 ;* Description        : STM32L496xx Ultra Low Power devices vector table for MDK-ARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -12,33 +10,18 @@
 ;*                        calls main()).
 ;*                      After Reset the Cortex-M4 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;*
+;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
+;*
+;*******************************************************************************
 ;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
-;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
-;*******************************************************************************
-;
 ; Amount of memory (in bytes) allocated for Stack
 ; Tailor this value to your application needs
 ; <h> Stack Configuration

CMSIS/STM32L4xx/Source/Templates/arm/startup_stm32l4a6xx.s

@@ -1,8 +1,6 @@
-;********************** COPYRIGHT(c) 2017  STMicroelectronics ******************
+;*******************************************************************************
 ;* File Name          : startup_stm32l4a6xx.s
 ;* Author             : MCD Application Team
-;* Version            : V1.3.2
-;* Date               : 16-June-2017
 ;* Description        : STM32L4A6xx Ultra Low Power devices vector table for MDK-ARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -12,33 +10,18 @@
 ;*                        calls main()).
 ;*                      After Reset the Cortex-M4 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;*
+;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
+;*
+;*******************************************************************************
 ;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
-;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
-;*******************************************************************************
-;
 ; Amount of memory (in bytes) allocated for Stack
 ; Tailor this value to your application needs
 ; <h> Stack Configuration

CMSIS/STM32L4xx/Source/Templates/arm/startup_stm32l4p5xx.s

@@ -0,0 +1,447 @@
+;*******************************************************************************
+;* File Name          : startup_stm32l4p5xx.s
+;* Author             : MCD Application Team
+;* Description        : STM32L4P5xx Ultra Low Power devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;*
+;* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
+;*
+;*******************************************************************************
+;* <<< Use Configuration Wizard in Context Menu >>>
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x400;
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x200;
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog
+                DCD     PVD_PVM_IRQHandler                ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+                DCD     FLASH_IRQHandler                  ; FLASH
+                DCD     RCC_IRQHandler                    ; RCC
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4
+                DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7
+                DCD     ADC1_2_IRQHandler                 ; ADC1, ADC2
+                DCD     CAN1_TX_IRQHandler                ; CAN1 TX
+                DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0
+                DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1
+                DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+                DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15
+                DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16
+                DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Commutation and TIM17
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler                   ; TIM2
+                DCD     TIM3_IRQHandler                   ; TIM3
+                DCD     TIM4_IRQHandler                   ; TIM4
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+                DCD     SPI1_IRQHandler                   ; SPI1
+                DCD     SPI2_IRQHandler                   ; SPI2
+                DCD     USART1_IRQHandler                 ; USART1
+                DCD     USART2_IRQHandler                 ; USART2
+                DCD     USART3_IRQHandler                 ; USART3
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+                DCD     0                                 ; Reserved
+                DCD     TIM8_BRK_IRQHandler               ; TIM8 Break Interrupt
+                DCD     TIM8_UP_IRQHandler                ; TIM8 Update Interrupt
+                DCD     TIM8_TRG_COM_IRQHandler           ; TIM8 Trigger and Commutation Interrupt
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt
+                DCD     SDMMC2_IRQHandler                 ; SDMMC2
+                DCD     FMC_IRQHandler                    ; FMC
+                DCD     SDMMC1_IRQHandler                 ; SDMMC1
+                DCD     TIM5_IRQHandler                   ; TIM5
+                DCD     SPI3_IRQHandler                   ; SPI3
+                DCD     UART4_IRQHandler                  ; UART4
+                DCD     UART5_IRQHandler                  ; UART5
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+                DCD     TIM7_IRQHandler                   ; TIM7
+                DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1
+                DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2
+                DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3
+                DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4
+                DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5
+                DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM1 Filter 0 global Interrupt
+                DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM1 Filter 1 global Interrupt
+                DCD     0                                 ; Reserved
+                DCD     COMP_IRQHandler                   ; COMP Interrupt
+                DCD     LPTIM1_IRQHandler                 ; LP TIM1 interrupt
+                DCD     LPTIM2_IRQHandler                 ; LP TIM2 interrupt
+                DCD     OTG_FS_IRQHandler                 ; USB OTG FS
+                DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6
+                DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7
+                DCD     LPUART1_IRQHandler                ; LP UART1 interrupt
+                DCD     OCTOSPI1_IRQHandler               ; OctoSPI1 global interrupt
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error
+                DCD     SAI1_IRQHandler                   ; Serial Audio Interface 1 global interrupt
+                DCD     SAI2_IRQHandler                   ; Serial Audio Interface 2 global interrupt
+                DCD     OCTOSPI2_IRQHandler               ; OctoSPI2 global interrupt
+                DCD     TSC_IRQHandler                    ; Touch Sense Controller global interrupt
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     RNG_IRQHandler                    ; RNG global interrupt
+                DCD     FPU_IRQHandler                    ; FPU
+                DCD     HASH_CRS_IRQHandler               ; HASH and CRS global interrupt
+                DCD     I2C4_ER_IRQHandler                ; I2C4 error
+                DCD     I2C4_EV_IRQHandler                ; I2C4 event
+                DCD     DCMI_PSSI_IRQHandler              ; DCMI and PSSI global global interrupt
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     DMA2D_IRQHandler                  ; DMA2D global interrupt
+                DCD     LTDC_IRQHandler                   ; LTDC global interrupt
+                DCD     LTDC_ER_IRQHandler                ; LTDC error global interrupt
+                DCD     0                                 ; Reserved
+                DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX1 overrun global interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+        EXPORT     WWDG_IRQHandler                   [WEAK]
+        EXPORT     PVD_PVM_IRQHandler                [WEAK]
+        EXPORT     TAMP_STAMP_IRQHandler             [WEAK]
+        EXPORT     RTC_WKUP_IRQHandler               [WEAK]
+        EXPORT     FLASH_IRQHandler                  [WEAK]
+        EXPORT     RCC_IRQHandler                    [WEAK]
+        EXPORT     EXTI0_IRQHandler                  [WEAK]
+        EXPORT     EXTI1_IRQHandler                  [WEAK]
+        EXPORT     EXTI2_IRQHandler                  [WEAK]
+        EXPORT     EXTI3_IRQHandler                  [WEAK]
+        EXPORT     EXTI4_IRQHandler                  [WEAK]
+        EXPORT     DMA1_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel5_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel7_IRQHandler          [WEAK]
+        EXPORT     ADC1_2_IRQHandler                 [WEAK]
+        EXPORT     CAN1_TX_IRQHandler                [WEAK]
+        EXPORT     CAN1_RX0_IRQHandler               [WEAK]
+        EXPORT     CAN1_RX1_IRQHandler               [WEAK]
+        EXPORT     CAN1_SCE_IRQHandler               [WEAK]
+        EXPORT     EXTI9_5_IRQHandler                [WEAK]
+        EXPORT     TIM1_BRK_TIM15_IRQHandler         [WEAK]
+        EXPORT     TIM1_UP_TIM16_IRQHandler          [WEAK]
+        EXPORT     TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+        EXPORT     TIM1_CC_IRQHandler                [WEAK]
+        EXPORT     TIM2_IRQHandler                   [WEAK]
+        EXPORT     TIM3_IRQHandler                   [WEAK]
+        EXPORT     TIM4_IRQHandler                   [WEAK]
+        EXPORT     I2C1_EV_IRQHandler                [WEAK]
+        EXPORT     I2C1_ER_IRQHandler                [WEAK]
+        EXPORT     I2C2_EV_IRQHandler                [WEAK]
+        EXPORT     I2C2_ER_IRQHandler                [WEAK]
+        EXPORT     SPI1_IRQHandler                   [WEAK]
+        EXPORT     SPI2_IRQHandler                   [WEAK]
+        EXPORT     USART1_IRQHandler                 [WEAK]
+        EXPORT     USART2_IRQHandler                 [WEAK]
+        EXPORT     USART3_IRQHandler                 [WEAK]
+        EXPORT     EXTI15_10_IRQHandler              [WEAK]
+        EXPORT     RTC_Alarm_IRQHandler              [WEAK]
+        EXPORT     TIM8_BRK_IRQHandler               [WEAK]
+        EXPORT     TIM8_UP_IRQHandler                [WEAK]
+        EXPORT     TIM8_TRG_COM_IRQHandler           [WEAK]
+        EXPORT     TIM8_CC_IRQHandler                [WEAK]
+        EXPORT     SDMMC2_IRQHandler                 [WEAK]
+        EXPORT     FMC_IRQHandler                    [WEAK]
+        EXPORT     SDMMC1_IRQHandler                 [WEAK]
+        EXPORT     TIM5_IRQHandler                   [WEAK]
+        EXPORT     SPI3_IRQHandler                   [WEAK]
+        EXPORT     UART4_IRQHandler                  [WEAK]
+        EXPORT     UART5_IRQHandler                  [WEAK]
+        EXPORT     TIM6_DAC_IRQHandler               [WEAK]
+        EXPORT     TIM7_IRQHandler                   [WEAK]
+        EXPORT     DMA2_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel5_IRQHandler          [WEAK]
+        EXPORT     DFSDM1_FLT0_IRQHandler            [WEAK]
+        EXPORT     DFSDM1_FLT1_IRQHandler            [WEAK]
+        EXPORT     COMP_IRQHandler                   [WEAK]
+        EXPORT     LPTIM1_IRQHandler                 [WEAK]
+        EXPORT     LPTIM2_IRQHandler                 [WEAK]
+        EXPORT     OTG_FS_IRQHandler                 [WEAK]
+        EXPORT     DMA2_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel7_IRQHandler          [WEAK]
+        EXPORT     LPUART1_IRQHandler                [WEAK]
+        EXPORT     OCTOSPI1_IRQHandler               [WEAK]
+        EXPORT     I2C3_EV_IRQHandler                [WEAK]
+        EXPORT     I2C3_ER_IRQHandler                [WEAK]
+        EXPORT     SAI1_IRQHandler                   [WEAK]
+        EXPORT     SAI2_IRQHandler                   [WEAK]
+        EXPORT     OCTOSPI2_IRQHandler               [WEAK]
+        EXPORT     TSC_IRQHandler                    [WEAK]
+        EXPORT     RNG_IRQHandler                    [WEAK]
+        EXPORT     FPU_IRQHandler                    [WEAK]
+        EXPORT     HASH_CRS_IRQHandler               [WEAK]
+        EXPORT     I2C4_ER_IRQHandler                [WEAK]
+        EXPORT     I2C4_EV_IRQHandler                [WEAK]
+        EXPORT     DCMI_PSSI_IRQHandler              [WEAK]
+        EXPORT     DMA2D_IRQHandler                  [WEAK]
+        EXPORT     LTDC_IRQHandler                   [WEAK]
+        EXPORT     LTDC_ER_IRQHandler                [WEAK]
+        EXPORT     DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+CAN1_TX_IRQHandler
+CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM15_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+TIM8_BRK_IRQHandler
+TIM8_UP_IRQHandler
+TIM8_TRG_COM_IRQHandler
+TIM8_CC_IRQHandler
+SDMMC2_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+COMP_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+OTG_FS_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+LPUART1_IRQHandler
+OCTOSPI1_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SAI1_IRQHandler
+SAI2_IRQHandler
+OCTOSPI2_IRQHandler
+TSC_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+HASH_CRS_IRQHandler
+I2C4_ER_IRQHandler
+I2C4_EV_IRQHandler
+DCMI_PSSI_IRQHandler
+DMA2D_IRQHandler
+LTDC_IRQHandler
+LTDC_ER_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

CMSIS/STM32L4xx/Source/Templates/arm/startup_stm32l4q5xx.s

@@ -0,0 +1,451 @@
+;*******************************************************************************
+;* File Name          : startup_stm32l4q5xx.s
+;* Author             : MCD Application Team
+;* Description        : STM32L4Q5xx Ultra Low Power devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;*
+;* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
+;*
+;*******************************************************************************
+;* <<< Use Configuration Wizard in Context Menu >>>
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x400;
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x200;
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog
+                DCD     PVD_PVM_IRQHandler                ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+                DCD     FLASH_IRQHandler                  ; FLASH
+                DCD     RCC_IRQHandler                    ; RCC
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4
+                DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7
+                DCD     ADC1_2_IRQHandler                 ; ADC1, ADC2
+                DCD     CAN1_TX_IRQHandler                ; CAN1 TX
+                DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0
+                DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1
+                DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+                DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15
+                DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16
+                DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Commutation and TIM17
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler                   ; TIM2
+                DCD     TIM3_IRQHandler                   ; TIM3
+                DCD     TIM4_IRQHandler                   ; TIM4
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+                DCD     SPI1_IRQHandler                   ; SPI1
+                DCD     SPI2_IRQHandler                   ; SPI2
+                DCD     USART1_IRQHandler                 ; USART1
+                DCD     USART2_IRQHandler                 ; USART2
+                DCD     USART3_IRQHandler                 ; USART3
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+                DCD     0                                 ; Reserved
+                DCD     TIM8_BRK_IRQHandler               ; TIM8 Break Interrupt
+                DCD     TIM8_UP_IRQHandler                ; TIM8 Update Interrupt
+                DCD     TIM8_TRG_COM_IRQHandler           ; TIM8 Trigger and Commutation Interrupt
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt
+                DCD     SDMMC2_IRQHandler                 ; SDMMC2
+                DCD     FMC_IRQHandler                    ; FMC
+                DCD     SDMMC1_IRQHandler                 ; SDMMC1
+                DCD     TIM5_IRQHandler                   ; TIM5
+                DCD     SPI3_IRQHandler                   ; SPI3
+                DCD     UART4_IRQHandler                  ; UART4
+                DCD     UART5_IRQHandler                  ; UART5
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+                DCD     TIM7_IRQHandler                   ; TIM7
+                DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1
+                DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2
+                DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3
+                DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4
+                DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5
+                DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM1 Filter 0 global Interrupt
+                DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM1 Filter 1 global Interrupt
+                DCD     0                                 ; Reserved
+                DCD     COMP_IRQHandler                   ; COMP Interrupt
+                DCD     LPTIM1_IRQHandler                 ; LP TIM1 interrupt
+                DCD     LPTIM2_IRQHandler                 ; LP TIM2 interrupt
+                DCD     OTG_FS_IRQHandler                 ; USB OTG FS
+                DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6
+                DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7
+                DCD     LPUART1_IRQHandler                ; LP UART1 interrupt
+                DCD     OCTOSPI1_IRQHandler               ; OctoSPI1 global interrupt
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error
+                DCD     SAI1_IRQHandler                   ; Serial Audio Interface 1 global interrupt
+                DCD     SAI2_IRQHandler                   ; Serial Audio Interface 2 global interrupt
+                DCD     OCTOSPI2_IRQHandler               ; OctoSPI2 global interrupt
+                DCD     TSC_IRQHandler                    ; Touch Sense Controller global interrupt
+                DCD     0                                 ; Reserved
+                DCD     AES_IRQHandler                    ; AES global interrupt
+                DCD     RNG_IRQHandler                    ; RNG global interrupt
+                DCD     FPU_IRQHandler                    ; FPU
+                DCD     HASH_CRS_IRQHandler               ; HASH and CRS global interrupt
+                DCD     I2C4_ER_IRQHandler                ; I2C4 error
+                DCD     I2C4_EV_IRQHandler                ; I2C4 event
+                DCD     DCMI_PSSI_IRQHandler              ; DCMI and PSSI global global interrupt
+                DCD     PKA_IRQHandler                    ; PKA global interrupt
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     DMA2D_IRQHandler                  ; DMA2D global interrupt
+                DCD     LTDC_IRQHandler                   ; LTDC global interrupt
+                DCD     LTDC_ER_IRQHandler                ; LTDC error global interrupt
+                DCD     0                                 ; Reserved
+                DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX1 overrun global interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+        EXPORT     WWDG_IRQHandler                   [WEAK]
+        EXPORT     PVD_PVM_IRQHandler                [WEAK]
+        EXPORT     TAMP_STAMP_IRQHandler             [WEAK]
+        EXPORT     RTC_WKUP_IRQHandler               [WEAK]
+        EXPORT     FLASH_IRQHandler                  [WEAK]
+        EXPORT     RCC_IRQHandler                    [WEAK]
+        EXPORT     EXTI0_IRQHandler                  [WEAK]
+        EXPORT     EXTI1_IRQHandler                  [WEAK]
+        EXPORT     EXTI2_IRQHandler                  [WEAK]
+        EXPORT     EXTI3_IRQHandler                  [WEAK]
+        EXPORT     EXTI4_IRQHandler                  [WEAK]
+        EXPORT     DMA1_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel5_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel7_IRQHandler          [WEAK]
+        EXPORT     ADC1_2_IRQHandler                 [WEAK]
+        EXPORT     CAN1_TX_IRQHandler                [WEAK]
+        EXPORT     CAN1_RX0_IRQHandler               [WEAK]
+        EXPORT     CAN1_RX1_IRQHandler               [WEAK]
+        EXPORT     CAN1_SCE_IRQHandler               [WEAK]
+        EXPORT     EXTI9_5_IRQHandler                [WEAK]
+        EXPORT     TIM1_BRK_TIM15_IRQHandler         [WEAK]
+        EXPORT     TIM1_UP_TIM16_IRQHandler          [WEAK]
+        EXPORT     TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+        EXPORT     TIM1_CC_IRQHandler                [WEAK]
+        EXPORT     TIM2_IRQHandler                   [WEAK]
+        EXPORT     TIM3_IRQHandler                   [WEAK]
+        EXPORT     TIM4_IRQHandler                   [WEAK]
+        EXPORT     I2C1_EV_IRQHandler                [WEAK]
+        EXPORT     I2C1_ER_IRQHandler                [WEAK]
+        EXPORT     I2C2_EV_IRQHandler                [WEAK]
+        EXPORT     I2C2_ER_IRQHandler                [WEAK]
+        EXPORT     SPI1_IRQHandler                   [WEAK]
+        EXPORT     SPI2_IRQHandler                   [WEAK]
+        EXPORT     USART1_IRQHandler                 [WEAK]
+        EXPORT     USART2_IRQHandler                 [WEAK]
+        EXPORT     USART3_IRQHandler                 [WEAK]
+        EXPORT     EXTI15_10_IRQHandler              [WEAK]
+        EXPORT     RTC_Alarm_IRQHandler              [WEAK]
+        EXPORT     TIM8_BRK_IRQHandler               [WEAK]
+        EXPORT     TIM8_UP_IRQHandler                [WEAK]
+        EXPORT     TIM8_TRG_COM_IRQHandler           [WEAK]
+        EXPORT     TIM8_CC_IRQHandler                [WEAK]
+        EXPORT     SDMMC2_IRQHandler                 [WEAK]
+        EXPORT     FMC_IRQHandler                    [WEAK]
+        EXPORT     SDMMC1_IRQHandler                 [WEAK]
+        EXPORT     TIM5_IRQHandler                   [WEAK]
+        EXPORT     SPI3_IRQHandler                   [WEAK]
+        EXPORT     UART4_IRQHandler                  [WEAK]
+        EXPORT     UART5_IRQHandler                  [WEAK]
+        EXPORT     TIM6_DAC_IRQHandler               [WEAK]
+        EXPORT     TIM7_IRQHandler                   [WEAK]
+        EXPORT     DMA2_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel5_IRQHandler          [WEAK]
+        EXPORT     DFSDM1_FLT0_IRQHandler            [WEAK]
+        EXPORT     DFSDM1_FLT1_IRQHandler            [WEAK]
+        EXPORT     COMP_IRQHandler                   [WEAK]
+        EXPORT     LPTIM1_IRQHandler                 [WEAK]
+        EXPORT     LPTIM2_IRQHandler                 [WEAK]
+        EXPORT     OTG_FS_IRQHandler                 [WEAK]
+        EXPORT     DMA2_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel7_IRQHandler          [WEAK]
+        EXPORT     LPUART1_IRQHandler                [WEAK]
+        EXPORT     OCTOSPI1_IRQHandler               [WEAK]
+        EXPORT     I2C3_EV_IRQHandler                [WEAK]
+        EXPORT     I2C3_ER_IRQHandler                [WEAK]
+        EXPORT     SAI1_IRQHandler                   [WEAK]
+        EXPORT     SAI2_IRQHandler                   [WEAK]
+        EXPORT     OCTOSPI2_IRQHandler               [WEAK]
+        EXPORT     TSC_IRQHandler                    [WEAK]
+        EXPORT     AES_IRQHandler                    [WEAK]
+        EXPORT     RNG_IRQHandler                    [WEAK]
+        EXPORT     FPU_IRQHandler                    [WEAK]
+        EXPORT     HASH_CRS_IRQHandler               [WEAK]
+        EXPORT     I2C4_ER_IRQHandler                [WEAK]
+        EXPORT     I2C4_EV_IRQHandler                [WEAK]
+        EXPORT     DCMI_PSSI_IRQHandler              [WEAK]
+        EXPORT     PKA_IRQHandler                    [WEAK]
+        EXPORT     DMA2D_IRQHandler                  [WEAK]
+        EXPORT     LTDC_IRQHandler                   [WEAK]
+        EXPORT     LTDC_ER_IRQHandler                [WEAK]
+        EXPORT     DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+CAN1_TX_IRQHandler
+CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM15_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+TIM8_BRK_IRQHandler
+TIM8_UP_IRQHandler
+TIM8_TRG_COM_IRQHandler
+TIM8_CC_IRQHandler
+SDMMC2_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+COMP_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+OTG_FS_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+LPUART1_IRQHandler
+OCTOSPI1_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SAI1_IRQHandler
+SAI2_IRQHandler
+OCTOSPI2_IRQHandler
+TSC_IRQHandler
+AES_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+HASH_CRS_IRQHandler
+I2C4_ER_IRQHandler
+I2C4_EV_IRQHandler
+DCMI_PSSI_IRQHandler
+PKA_IRQHandler
+DMA2D_IRQHandler
+LTDC_IRQHandler
+LTDC_ER_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

CMSIS/STM32L4xx/Source/Templates/arm/startup_stm32l4r5xx.s

@@ -0,0 +1,449 @@
+;*******************************************************************************
+;* File Name          : startup_stm32l4r5xx.s
+;* Author             : MCD Application Team
+;* Description        : STM32L4R5xx Ultra Low Power devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;*
+;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
+;*
+;*******************************************************************************
+;* <<< Use Configuration Wizard in Context Menu >>>
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x400;
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x200;
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog
+                DCD     PVD_PVM_IRQHandler                ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+                DCD     FLASH_IRQHandler                  ; FLASH
+                DCD     RCC_IRQHandler                    ; RCC
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4
+                DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7
+                DCD     ADC1_IRQHandler                   ; ADC1
+                DCD     CAN1_TX_IRQHandler                ; CAN1 TX
+                DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0
+                DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1
+                DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+                DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15
+                DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16
+                DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Commutation and TIM17
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler                   ; TIM2
+                DCD     TIM3_IRQHandler                   ; TIM3
+                DCD     TIM4_IRQHandler                   ; TIM4
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+                DCD     SPI1_IRQHandler                   ; SPI1
+                DCD     SPI2_IRQHandler                   ; SPI2
+                DCD     USART1_IRQHandler                 ; USART1
+                DCD     USART2_IRQHandler                 ; USART2
+                DCD     USART3_IRQHandler                 ; USART3
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+                DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM1 Filter 3 global Interrupt
+                DCD     TIM8_BRK_IRQHandler               ; TIM8 Break Interrupt
+                DCD     TIM8_UP_IRQHandler                ; TIM8 Update Interrupt
+                DCD     TIM8_TRG_COM_IRQHandler           ; TIM8 Trigger and Commutation Interrupt
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt
+                DCD     0                                 ; Reserved
+                DCD     FMC_IRQHandler                    ; FMC
+                DCD     SDMMC1_IRQHandler                 ; SDMMC1
+                DCD     TIM5_IRQHandler                   ; TIM5
+                DCD     SPI3_IRQHandler                   ; SPI3
+                DCD     UART4_IRQHandler                  ; UART4
+                DCD     UART5_IRQHandler                  ; UART5
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+                DCD     TIM7_IRQHandler                   ; TIM7
+                DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1
+                DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2
+                DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3
+                DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4
+                DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5
+                DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM1 Filter 0 global Interrupt
+                DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM1 Filter 1 global Interrupt
+                DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM1 Filter 2 global Interrupt
+                DCD     COMP_IRQHandler                   ; COMP Interrupt
+                DCD     LPTIM1_IRQHandler                 ; LP TIM1 interrupt
+                DCD     LPTIM2_IRQHandler                 ; LP TIM2 interrupt
+                DCD     OTG_FS_IRQHandler                 ; USB OTG FS
+                DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6
+                DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7
+                DCD     LPUART1_IRQHandler                ; LP UART1 interrupt
+                DCD     OCTOSPI1_IRQHandler               ; OctoSPI1 global interrupt
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error
+                DCD     SAI1_IRQHandler                   ; Serial Audio Interface 1 global interrupt
+                DCD     SAI2_IRQHandler                   ; Serial Audio Interface 2 global interrupt
+                DCD     OCTOSPI2_IRQHandler               ; OctoSPI2 global interrupt
+                DCD     TSC_IRQHandler                    ; Touch Sense Controller global interrupt
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     RNG_IRQHandler                    ; RNG global interrupt
+                DCD     FPU_IRQHandler                    ; FPU
+                DCD     CRS_IRQHandler                    ; CRS global interrupt
+                DCD     I2C4_ER_IRQHandler                ; I2C4 error
+                DCD     I2C4_EV_IRQHandler                ; I2C4 event
+                DCD     DCMI_IRQHandler                   ; DCMI global interrupt
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     DMA2D_IRQHandler                  ; DMA2D global interrupt
+                DCD     LTDC_IRQHandler                   ; LTDC global interrupt
+                DCD     LTDC_ER_IRQHandler                ; LTDC error global interrupt
+                DCD     GFXMMU_IRQHandler                 ; GFXMMU global interrupt
+                DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX1 overrun global interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+        EXPORT     WWDG_IRQHandler                   [WEAK]
+        EXPORT     PVD_PVM_IRQHandler                [WEAK]
+        EXPORT     TAMP_STAMP_IRQHandler             [WEAK]
+        EXPORT     RTC_WKUP_IRQHandler               [WEAK]
+        EXPORT     FLASH_IRQHandler                  [WEAK]
+        EXPORT     RCC_IRQHandler                    [WEAK]
+        EXPORT     EXTI0_IRQHandler                  [WEAK]
+        EXPORT     EXTI1_IRQHandler                  [WEAK]
+        EXPORT     EXTI2_IRQHandler                  [WEAK]
+        EXPORT     EXTI3_IRQHandler                  [WEAK]
+        EXPORT     EXTI4_IRQHandler                  [WEAK]
+        EXPORT     DMA1_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel5_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel7_IRQHandler          [WEAK]
+        EXPORT     ADC1_IRQHandler                   [WEAK]
+        EXPORT     CAN1_TX_IRQHandler                [WEAK]
+        EXPORT     CAN1_RX0_IRQHandler               [WEAK]
+        EXPORT     CAN1_RX1_IRQHandler               [WEAK]
+        EXPORT     CAN1_SCE_IRQHandler               [WEAK]
+        EXPORT     EXTI9_5_IRQHandler                [WEAK]
+        EXPORT     TIM1_BRK_TIM15_IRQHandler         [WEAK]
+        EXPORT     TIM1_UP_TIM16_IRQHandler          [WEAK]
+        EXPORT     TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+        EXPORT     TIM1_CC_IRQHandler                [WEAK]
+        EXPORT     TIM2_IRQHandler                   [WEAK]
+        EXPORT     TIM3_IRQHandler                   [WEAK]
+        EXPORT     TIM4_IRQHandler                   [WEAK]
+        EXPORT     I2C1_EV_IRQHandler                [WEAK]
+        EXPORT     I2C1_ER_IRQHandler                [WEAK]
+        EXPORT     I2C2_EV_IRQHandler                [WEAK]
+        EXPORT     I2C2_ER_IRQHandler                [WEAK]
+        EXPORT     SPI1_IRQHandler                   [WEAK]
+        EXPORT     SPI2_IRQHandler                   [WEAK]
+        EXPORT     USART1_IRQHandler                 [WEAK]
+        EXPORT     USART2_IRQHandler                 [WEAK]
+        EXPORT     USART3_IRQHandler                 [WEAK]
+        EXPORT     EXTI15_10_IRQHandler              [WEAK]
+        EXPORT     RTC_Alarm_IRQHandler              [WEAK]
+        EXPORT     DFSDM1_FLT3_IRQHandler            [WEAK]
+        EXPORT     TIM8_BRK_IRQHandler               [WEAK]
+        EXPORT     TIM8_UP_IRQHandler                [WEAK]
+        EXPORT     TIM8_TRG_COM_IRQHandler           [WEAK]
+        EXPORT     TIM8_CC_IRQHandler                [WEAK]
+        EXPORT     FMC_IRQHandler                    [WEAK]
+        EXPORT     SDMMC1_IRQHandler                 [WEAK]
+        EXPORT     TIM5_IRQHandler                   [WEAK]
+        EXPORT     SPI3_IRQHandler                   [WEAK]
+        EXPORT     UART4_IRQHandler                  [WEAK]
+        EXPORT     UART5_IRQHandler                  [WEAK]
+        EXPORT     TIM6_DAC_IRQHandler               [WEAK]
+        EXPORT     TIM7_IRQHandler                   [WEAK]
+        EXPORT     DMA2_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel5_IRQHandler          [WEAK]
+        EXPORT     DFSDM1_FLT0_IRQHandler            [WEAK]
+        EXPORT     DFSDM1_FLT1_IRQHandler            [WEAK]
+        EXPORT     DFSDM1_FLT2_IRQHandler            [WEAK]
+        EXPORT     COMP_IRQHandler                   [WEAK]
+        EXPORT     LPTIM1_IRQHandler                 [WEAK]
+        EXPORT     LPTIM2_IRQHandler                 [WEAK]
+        EXPORT     OTG_FS_IRQHandler                 [WEAK]
+        EXPORT     DMA2_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel7_IRQHandler          [WEAK]
+        EXPORT     LPUART1_IRQHandler                [WEAK]
+        EXPORT     OCTOSPI1_IRQHandler               [WEAK]
+        EXPORT     I2C3_EV_IRQHandler                [WEAK]
+        EXPORT     I2C3_ER_IRQHandler                [WEAK]
+        EXPORT     SAI1_IRQHandler                   [WEAK]
+        EXPORT     SAI2_IRQHandler                   [WEAK]
+        EXPORT     OCTOSPI2_IRQHandler               [WEAK]
+        EXPORT     TSC_IRQHandler                    [WEAK]
+        EXPORT     RNG_IRQHandler                    [WEAK]
+        EXPORT     FPU_IRQHandler                    [WEAK]
+        EXPORT     CRS_IRQHandler                    [WEAK]
+        EXPORT     I2C4_ER_IRQHandler                [WEAK]
+        EXPORT     I2C4_EV_IRQHandler                [WEAK]
+        EXPORT     DCMI_IRQHandler                   [WEAK]
+        EXPORT     DMA2D_IRQHandler                  [WEAK]
+        EXPORT     LTDC_IRQHandler                   [WEAK]
+        EXPORT     LTDC_ER_IRQHandler                [WEAK]
+        EXPORT     GFXMMU_IRQHandler                 [WEAK]
+        EXPORT     DMAMUX1_OVR_IRQHandler             [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+CAN1_TX_IRQHandler
+CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM15_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+DFSDM1_FLT3_IRQHandler
+TIM8_BRK_IRQHandler
+TIM8_UP_IRQHandler
+TIM8_TRG_COM_IRQHandler
+TIM8_CC_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+COMP_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+OTG_FS_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+LPUART1_IRQHandler
+OCTOSPI1_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SAI1_IRQHandler
+SAI2_IRQHandler
+OCTOSPI2_IRQHandler
+TSC_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+CRS_IRQHandler
+I2C4_ER_IRQHandler
+I2C4_EV_IRQHandler
+DCMI_IRQHandler
+DMA2D_IRQHandler
+LTDC_IRQHandler
+LTDC_ER_IRQHandler
+GFXMMU_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

CMSIS/STM32L4xx/Source/Templates/arm/startup_stm32l4r7xx.s

@@ -0,0 +1,449 @@
+;*******************************************************************************
+;* File Name          : startup_stm32l4r7xx.s
+;* Author             : MCD Application Team
+;* Description        : STM32L4R7xx Ultra Low Power devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;*
+;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
+;*
+;*******************************************************************************
+;* <<< Use Configuration Wizard in Context Menu >>>
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x400;
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x200;
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog
+                DCD     PVD_PVM_IRQHandler                ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+                DCD     FLASH_IRQHandler                  ; FLASH
+                DCD     RCC_IRQHandler                    ; RCC
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4
+                DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7
+                DCD     ADC1_IRQHandler                   ; ADC1
+                DCD     CAN1_TX_IRQHandler                ; CAN1 TX
+                DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0
+                DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1
+                DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+                DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15
+                DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16
+                DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Commutation and TIM17
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler                   ; TIM2
+                DCD     TIM3_IRQHandler                   ; TIM3
+                DCD     TIM4_IRQHandler                   ; TIM4
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+                DCD     SPI1_IRQHandler                   ; SPI1
+                DCD     SPI2_IRQHandler                   ; SPI2
+                DCD     USART1_IRQHandler                 ; USART1
+                DCD     USART2_IRQHandler                 ; USART2
+                DCD     USART3_IRQHandler                 ; USART3
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+                DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM1 Filter 3 global Interrupt
+                DCD     TIM8_BRK_IRQHandler               ; TIM8 Break Interrupt
+                DCD     TIM8_UP_IRQHandler                ; TIM8 Update Interrupt
+                DCD     TIM8_TRG_COM_IRQHandler           ; TIM8 Trigger and Commutation Interrupt
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt
+                DCD     0                                 ; Reserved
+                DCD     FMC_IRQHandler                    ; FMC
+                DCD     SDMMC1_IRQHandler                 ; SDMMC1
+                DCD     TIM5_IRQHandler                   ; TIM5
+                DCD     SPI3_IRQHandler                   ; SPI3
+                DCD     UART4_IRQHandler                  ; UART4
+                DCD     UART5_IRQHandler                  ; UART5
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+                DCD     TIM7_IRQHandler                   ; TIM7
+                DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1
+                DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2
+                DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3
+                DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4
+                DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5
+                DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM1 Filter 0 global Interrupt
+                DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM1 Filter 1 global Interrupt
+                DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM1 Filter 2 global Interrupt
+                DCD     COMP_IRQHandler                   ; COMP Interrupt
+                DCD     LPTIM1_IRQHandler                 ; LP TIM1 interrupt
+                DCD     LPTIM2_IRQHandler                 ; LP TIM2 interrupt
+                DCD     OTG_FS_IRQHandler                 ; USB OTG FS
+                DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6
+                DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7
+                DCD     LPUART1_IRQHandler                ; LP UART1 interrupt
+                DCD     OCTOSPI1_IRQHandler               ; OctoSPI1 global interrupt
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error
+                DCD     SAI1_IRQHandler                   ; Serial Audio Interface 1 global interrupt
+                DCD     SAI2_IRQHandler                   ; Serial Audio Interface 2 global interrupt
+                DCD     OCTOSPI2_IRQHandler               ; OctoSPI2 global interrupt
+                DCD     TSC_IRQHandler                    ; Touch Sense Controller global interrupt
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     RNG_IRQHandler                    ; RNG global interrupt
+                DCD     FPU_IRQHandler                    ; FPU
+                DCD     CRS_IRQHandler                    ; CRS global interrupt
+                DCD     I2C4_ER_IRQHandler                ; I2C4 error
+                DCD     I2C4_EV_IRQHandler                ; I2C4 event
+                DCD     DCMI_IRQHandler                   ; DCMI global interrupt
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     DMA2D_IRQHandler                  ; DMA2D global interrupt
+                DCD     LTDC_IRQHandler                   ; LTDC global interrupt
+                DCD     LTDC_ER_IRQHandler                ; LTDC error global interrupt
+                DCD     GFXMMU_IRQHandler                 ; GFXMMU global interrupt
+                DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX1 overrun global interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+        EXPORT     WWDG_IRQHandler                   [WEAK]
+        EXPORT     PVD_PVM_IRQHandler                [WEAK]
+        EXPORT     TAMP_STAMP_IRQHandler             [WEAK]
+        EXPORT     RTC_WKUP_IRQHandler               [WEAK]
+        EXPORT     FLASH_IRQHandler                  [WEAK]
+        EXPORT     RCC_IRQHandler                    [WEAK]
+        EXPORT     EXTI0_IRQHandler                  [WEAK]
+        EXPORT     EXTI1_IRQHandler                  [WEAK]
+        EXPORT     EXTI2_IRQHandler                  [WEAK]
+        EXPORT     EXTI3_IRQHandler                  [WEAK]
+        EXPORT     EXTI4_IRQHandler                  [WEAK]
+        EXPORT     DMA1_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel5_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel7_IRQHandler          [WEAK]
+        EXPORT     ADC1_IRQHandler                   [WEAK]
+        EXPORT     CAN1_TX_IRQHandler                [WEAK]
+        EXPORT     CAN1_RX0_IRQHandler               [WEAK]
+        EXPORT     CAN1_RX1_IRQHandler               [WEAK]
+        EXPORT     CAN1_SCE_IRQHandler               [WEAK]
+        EXPORT     EXTI9_5_IRQHandler                [WEAK]
+        EXPORT     TIM1_BRK_TIM15_IRQHandler         [WEAK]
+        EXPORT     TIM1_UP_TIM16_IRQHandler          [WEAK]
+        EXPORT     TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+        EXPORT     TIM1_CC_IRQHandler                [WEAK]
+        EXPORT     TIM2_IRQHandler                   [WEAK]
+        EXPORT     TIM3_IRQHandler                   [WEAK]
+        EXPORT     TIM4_IRQHandler                   [WEAK]
+        EXPORT     I2C1_EV_IRQHandler                [WEAK]
+        EXPORT     I2C1_ER_IRQHandler                [WEAK]
+        EXPORT     I2C2_EV_IRQHandler                [WEAK]
+        EXPORT     I2C2_ER_IRQHandler                [WEAK]
+        EXPORT     SPI1_IRQHandler                   [WEAK]
+        EXPORT     SPI2_IRQHandler                   [WEAK]
+        EXPORT     USART1_IRQHandler                 [WEAK]
+        EXPORT     USART2_IRQHandler                 [WEAK]
+        EXPORT     USART3_IRQHandler                 [WEAK]
+        EXPORT     EXTI15_10_IRQHandler              [WEAK]
+        EXPORT     RTC_Alarm_IRQHandler              [WEAK]
+        EXPORT     DFSDM1_FLT3_IRQHandler            [WEAK]
+        EXPORT     TIM8_BRK_IRQHandler               [WEAK]
+        EXPORT     TIM8_UP_IRQHandler                [WEAK]
+        EXPORT     TIM8_TRG_COM_IRQHandler           [WEAK]
+        EXPORT     TIM8_CC_IRQHandler                [WEAK]
+        EXPORT     FMC_IRQHandler                    [WEAK]
+        EXPORT     SDMMC1_IRQHandler                 [WEAK]
+        EXPORT     TIM5_IRQHandler                   [WEAK]
+        EXPORT     SPI3_IRQHandler                   [WEAK]
+        EXPORT     UART4_IRQHandler                  [WEAK]
+        EXPORT     UART5_IRQHandler                  [WEAK]
+        EXPORT     TIM6_DAC_IRQHandler               [WEAK]
+        EXPORT     TIM7_IRQHandler                   [WEAK]
+        EXPORT     DMA2_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel5_IRQHandler          [WEAK]
+        EXPORT     DFSDM1_FLT0_IRQHandler            [WEAK]
+        EXPORT     DFSDM1_FLT1_IRQHandler            [WEAK]
+        EXPORT     DFSDM1_FLT2_IRQHandler            [WEAK]
+        EXPORT     COMP_IRQHandler                   [WEAK]
+        EXPORT     LPTIM1_IRQHandler                 [WEAK]
+        EXPORT     LPTIM2_IRQHandler                 [WEAK]
+        EXPORT     OTG_FS_IRQHandler                 [WEAK]
+        EXPORT     DMA2_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel7_IRQHandler          [WEAK]
+        EXPORT     LPUART1_IRQHandler                [WEAK]
+        EXPORT     OCTOSPI1_IRQHandler               [WEAK]
+        EXPORT     I2C3_EV_IRQHandler                [WEAK]
+        EXPORT     I2C3_ER_IRQHandler                [WEAK]
+        EXPORT     SAI1_IRQHandler                   [WEAK]
+        EXPORT     SAI2_IRQHandler                   [WEAK]
+        EXPORT     OCTOSPI2_IRQHandler               [WEAK]
+        EXPORT     TSC_IRQHandler                    [WEAK]
+        EXPORT     RNG_IRQHandler                    [WEAK]
+        EXPORT     FPU_IRQHandler                    [WEAK]
+        EXPORT     CRS_IRQHandler                    [WEAK]
+        EXPORT     I2C4_ER_IRQHandler                [WEAK]
+        EXPORT     I2C4_EV_IRQHandler                [WEAK]
+        EXPORT     DCMI_IRQHandler                   [WEAK]
+        EXPORT     DMA2D_IRQHandler                  [WEAK]
+        EXPORT     LTDC_IRQHandler                   [WEAK]
+        EXPORT     LTDC_ER_IRQHandler                [WEAK]
+        EXPORT     GFXMMU_IRQHandler                 [WEAK]
+        EXPORT     DMAMUX1_OVR_IRQHandler             [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+CAN1_TX_IRQHandler
+CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM15_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+DFSDM1_FLT3_IRQHandler
+TIM8_BRK_IRQHandler
+TIM8_UP_IRQHandler
+TIM8_TRG_COM_IRQHandler
+TIM8_CC_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+COMP_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+OTG_FS_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+LPUART1_IRQHandler
+OCTOSPI1_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SAI1_IRQHandler
+SAI2_IRQHandler
+OCTOSPI2_IRQHandler
+TSC_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+CRS_IRQHandler
+I2C4_ER_IRQHandler
+I2C4_EV_IRQHandler
+DCMI_IRQHandler
+DMA2D_IRQHandler
+LTDC_IRQHandler
+LTDC_ER_IRQHandler
+GFXMMU_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

CMSIS/STM32L4xx/Source/Templates/arm/startup_stm32l4r9xx.s

@@ -0,0 +1,451 @@
+;*******************************************************************************
+;* File Name          : startup_stm32l4r9xx.s
+;* Author             : MCD Application Team
+;* Description        : STM32L4R9xx Ultra Low Power devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;*
+;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
+;*
+;*******************************************************************************
+;* <<< Use Configuration Wizard in Context Menu >>>
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x400;
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x200;
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog
+                DCD     PVD_PVM_IRQHandler                ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+                DCD     FLASH_IRQHandler                  ; FLASH
+                DCD     RCC_IRQHandler                    ; RCC
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4
+                DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7
+                DCD     ADC1_IRQHandler                   ; ADC1
+                DCD     CAN1_TX_IRQHandler                ; CAN1 TX
+                DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0
+                DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1
+                DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+                DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15
+                DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16
+                DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Commutation and TIM17
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler                   ; TIM2
+                DCD     TIM3_IRQHandler                   ; TIM3
+                DCD     TIM4_IRQHandler                   ; TIM4
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+                DCD     SPI1_IRQHandler                   ; SPI1
+                DCD     SPI2_IRQHandler                   ; SPI2
+                DCD     USART1_IRQHandler                 ; USART1
+                DCD     USART2_IRQHandler                 ; USART2
+                DCD     USART3_IRQHandler                 ; USART3
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+                DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM1 Filter 3 global Interrupt
+                DCD     TIM8_BRK_IRQHandler               ; TIM8 Break Interrupt
+                DCD     TIM8_UP_IRQHandler                ; TIM8 Update Interrupt
+                DCD     TIM8_TRG_COM_IRQHandler           ; TIM8 Trigger and Commutation Interrupt
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt
+                DCD     0                                 ; Reserved
+                DCD     FMC_IRQHandler                    ; FMC
+                DCD     SDMMC1_IRQHandler                 ; SDMMC1
+                DCD     TIM5_IRQHandler                   ; TIM5
+                DCD     SPI3_IRQHandler                   ; SPI3
+                DCD     UART4_IRQHandler                  ; UART4
+                DCD     UART5_IRQHandler                  ; UART5
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+                DCD     TIM7_IRQHandler                   ; TIM7
+                DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1
+                DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2
+                DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3
+                DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4
+                DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5
+                DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM1 Filter 0 global Interrupt
+                DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM1 Filter 1 global Interrupt
+                DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM1 Filter 2 global Interrupt
+                DCD     COMP_IRQHandler                   ; COMP Interrupt
+                DCD     LPTIM1_IRQHandler                 ; LP TIM1 interrupt
+                DCD     LPTIM2_IRQHandler                 ; LP TIM2 interrupt
+                DCD     OTG_FS_IRQHandler                 ; USB OTG FS
+                DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6
+                DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7
+                DCD     LPUART1_IRQHandler                ; LP UART1 interrupt
+                DCD     OCTOSPI1_IRQHandler               ; OctoSPI1 global interrupt
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error
+                DCD     SAI1_IRQHandler                   ; Serial Audio Interface 1 global interrupt
+                DCD     SAI2_IRQHandler                   ; Serial Audio Interface 2 global interrupt
+                DCD     OCTOSPI2_IRQHandler               ; OctoSPI2 global interrupt
+                DCD     TSC_IRQHandler                    ; Touch Sense Controller global interrupt
+                DCD     DSI_IRQHandler                    ; DSI global interrupt
+                DCD     0                                 ; Reserved
+                DCD     RNG_IRQHandler                    ; RNG global interrupt
+                DCD     FPU_IRQHandler                    ; FPU
+                DCD     CRS_IRQHandler                    ; CRS global interrupt
+                DCD     I2C4_ER_IRQHandler                ; I2C4 error
+                DCD     I2C4_EV_IRQHandler                ; I2C4 event
+                DCD     DCMI_IRQHandler                   ; DCMI global interrupt
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     DMA2D_IRQHandler                  ; DMA2D global interrupt
+                DCD     LTDC_IRQHandler                   ; LTDC global interrupt
+                DCD     LTDC_ER_IRQHandler                ; LTDC error global interrupt
+                DCD     GFXMMU_IRQHandler                 ; GFXMMU global interrupt
+                DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX1 overrun global interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+        EXPORT     WWDG_IRQHandler                   [WEAK]
+        EXPORT     PVD_PVM_IRQHandler                [WEAK]
+        EXPORT     TAMP_STAMP_IRQHandler             [WEAK]
+        EXPORT     RTC_WKUP_IRQHandler               [WEAK]
+        EXPORT     FLASH_IRQHandler                  [WEAK]
+        EXPORT     RCC_IRQHandler                    [WEAK]
+        EXPORT     EXTI0_IRQHandler                  [WEAK]
+        EXPORT     EXTI1_IRQHandler                  [WEAK]
+        EXPORT     EXTI2_IRQHandler                  [WEAK]
+        EXPORT     EXTI3_IRQHandler                  [WEAK]
+        EXPORT     EXTI4_IRQHandler                  [WEAK]
+        EXPORT     DMA1_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel5_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel7_IRQHandler          [WEAK]
+        EXPORT     ADC1_IRQHandler                   [WEAK]
+        EXPORT     CAN1_TX_IRQHandler                [WEAK]
+        EXPORT     CAN1_RX0_IRQHandler               [WEAK]
+        EXPORT     CAN1_RX1_IRQHandler               [WEAK]
+        EXPORT     CAN1_SCE_IRQHandler               [WEAK]
+        EXPORT     EXTI9_5_IRQHandler                [WEAK]
+        EXPORT     TIM1_BRK_TIM15_IRQHandler         [WEAK]
+        EXPORT     TIM1_UP_TIM16_IRQHandler          [WEAK]
+        EXPORT     TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+        EXPORT     TIM1_CC_IRQHandler                [WEAK]
+        EXPORT     TIM2_IRQHandler                   [WEAK]
+        EXPORT     TIM3_IRQHandler                   [WEAK]
+        EXPORT     TIM4_IRQHandler                   [WEAK]
+        EXPORT     I2C1_EV_IRQHandler                [WEAK]
+        EXPORT     I2C1_ER_IRQHandler                [WEAK]
+        EXPORT     I2C2_EV_IRQHandler                [WEAK]
+        EXPORT     I2C2_ER_IRQHandler                [WEAK]
+        EXPORT     SPI1_IRQHandler                   [WEAK]
+        EXPORT     SPI2_IRQHandler                   [WEAK]
+        EXPORT     USART1_IRQHandler                 [WEAK]
+        EXPORT     USART2_IRQHandler                 [WEAK]
+        EXPORT     USART3_IRQHandler                 [WEAK]
+        EXPORT     EXTI15_10_IRQHandler              [WEAK]
+        EXPORT     RTC_Alarm_IRQHandler              [WEAK]
+        EXPORT     DFSDM1_FLT3_IRQHandler            [WEAK]
+        EXPORT     TIM8_BRK_IRQHandler               [WEAK]
+        EXPORT     TIM8_UP_IRQHandler                [WEAK]
+        EXPORT     TIM8_TRG_COM_IRQHandler           [WEAK]
+        EXPORT     TIM8_CC_IRQHandler                [WEAK]
+        EXPORT     FMC_IRQHandler                    [WEAK]
+        EXPORT     SDMMC1_IRQHandler                 [WEAK]
+        EXPORT     TIM5_IRQHandler                   [WEAK]
+        EXPORT     SPI3_IRQHandler                   [WEAK]
+        EXPORT     UART4_IRQHandler                  [WEAK]
+        EXPORT     UART5_IRQHandler                  [WEAK]
+        EXPORT     TIM6_DAC_IRQHandler               [WEAK]
+        EXPORT     TIM7_IRQHandler                   [WEAK]
+        EXPORT     DMA2_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel5_IRQHandler          [WEAK]
+        EXPORT     DFSDM1_FLT0_IRQHandler            [WEAK]
+        EXPORT     DFSDM1_FLT1_IRQHandler            [WEAK]
+        EXPORT     DFSDM1_FLT2_IRQHandler            [WEAK]
+        EXPORT     COMP_IRQHandler                   [WEAK]
+        EXPORT     LPTIM1_IRQHandler                 [WEAK]
+        EXPORT     LPTIM2_IRQHandler                 [WEAK]
+        EXPORT     OTG_FS_IRQHandler                 [WEAK]
+        EXPORT     DMA2_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel7_IRQHandler          [WEAK]
+        EXPORT     LPUART1_IRQHandler                [WEAK]
+        EXPORT     OCTOSPI1_IRQHandler               [WEAK]
+        EXPORT     I2C3_EV_IRQHandler                [WEAK]
+        EXPORT     I2C3_ER_IRQHandler                [WEAK]
+        EXPORT     SAI1_IRQHandler                   [WEAK]
+        EXPORT     SAI2_IRQHandler                   [WEAK]
+        EXPORT     OCTOSPI2_IRQHandler               [WEAK]
+        EXPORT     TSC_IRQHandler                    [WEAK]
+        EXPORT     DSI_IRQHandler                    [WEAK]
+        EXPORT     RNG_IRQHandler                    [WEAK]
+        EXPORT     FPU_IRQHandler                    [WEAK]
+        EXPORT     CRS_IRQHandler                    [WEAK]
+        EXPORT     I2C4_ER_IRQHandler                [WEAK]
+        EXPORT     I2C4_EV_IRQHandler                [WEAK]
+        EXPORT     DCMI_IRQHandler                   [WEAK]
+        EXPORT     DMA2D_IRQHandler                  [WEAK]
+        EXPORT     LTDC_IRQHandler                   [WEAK]
+        EXPORT     LTDC_ER_IRQHandler                [WEAK]
+        EXPORT     GFXMMU_IRQHandler                 [WEAK]
+        EXPORT     DMAMUX1_OVR_IRQHandler             [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+CAN1_TX_IRQHandler
+CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM15_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+DFSDM1_FLT3_IRQHandler
+TIM8_BRK_IRQHandler
+TIM8_UP_IRQHandler
+TIM8_TRG_COM_IRQHandler
+TIM8_CC_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+COMP_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+OTG_FS_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+LPUART1_IRQHandler
+OCTOSPI1_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SAI1_IRQHandler
+SAI2_IRQHandler
+OCTOSPI2_IRQHandler
+TSC_IRQHandler
+DSI_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+CRS_IRQHandler
+I2C4_ER_IRQHandler
+I2C4_EV_IRQHandler
+DCMI_IRQHandler
+DMA2D_IRQHandler
+LTDC_IRQHandler
+LTDC_ER_IRQHandler
+GFXMMU_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

CMSIS/STM32L4xx/Source/Templates/arm/startup_stm32l4s5xx.s

@@ -0,0 +1,451 @@
+;*******************************************************************************
+;* File Name          : startup_stm32l4s5xx.s
+;* Author             : MCD Application Team
+;* Description        : STM32L4S5xx Ultra Low Power devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;*
+;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
+;*
+;*******************************************************************************
+;* <<< Use Configuration Wizard in Context Menu >>>
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x400;
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x200;
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog
+                DCD     PVD_PVM_IRQHandler                ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+                DCD     FLASH_IRQHandler                  ; FLASH
+                DCD     RCC_IRQHandler                    ; RCC
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4
+                DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7
+                DCD     ADC1_IRQHandler                   ; ADC1
+                DCD     CAN1_TX_IRQHandler                ; CAN1 TX
+                DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0
+                DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1
+                DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+                DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15
+                DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16
+                DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Commutation and TIM17
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler                   ; TIM2
+                DCD     TIM3_IRQHandler                   ; TIM3
+                DCD     TIM4_IRQHandler                   ; TIM4
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+                DCD     SPI1_IRQHandler                   ; SPI1
+                DCD     SPI2_IRQHandler                   ; SPI2
+                DCD     USART1_IRQHandler                 ; USART1
+                DCD     USART2_IRQHandler                 ; USART2
+                DCD     USART3_IRQHandler                 ; USART3
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+                DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM1 Filter 3 global Interrupt
+                DCD     TIM8_BRK_IRQHandler               ; TIM8 Break Interrupt
+                DCD     TIM8_UP_IRQHandler                ; TIM8 Update Interrupt
+                DCD     TIM8_TRG_COM_IRQHandler           ; TIM8 Trigger and Commutation Interrupt
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt
+                DCD     0                                 ; Reserved
+                DCD     FMC_IRQHandler                    ; FMC
+                DCD     SDMMC1_IRQHandler                 ; SDMMC1
+                DCD     TIM5_IRQHandler                   ; TIM5
+                DCD     SPI3_IRQHandler                   ; SPI3
+                DCD     UART4_IRQHandler                  ; UART4
+                DCD     UART5_IRQHandler                  ; UART5
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+                DCD     TIM7_IRQHandler                   ; TIM7
+                DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1
+                DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2
+                DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3
+                DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4
+                DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5
+                DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM1 Filter 0 global Interrupt
+                DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM1 Filter 1 global Interrupt
+                DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM1 Filter 2 global Interrupt
+                DCD     COMP_IRQHandler                   ; COMP Interrupt
+                DCD     LPTIM1_IRQHandler                 ; LP TIM1 interrupt
+                DCD     LPTIM2_IRQHandler                 ; LP TIM2 interrupt
+                DCD     OTG_FS_IRQHandler                 ; USB OTG FS
+                DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6
+                DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7
+                DCD     LPUART1_IRQHandler                ; LP UART1 interrupt
+                DCD     OCTOSPI1_IRQHandler               ; OctoSPI1 global interrupt
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error
+                DCD     SAI1_IRQHandler                   ; Serial Audio Interface 1 global interrupt
+                DCD     SAI2_IRQHandler                   ; Serial Audio Interface 2 global interrupt
+                DCD     OCTOSPI2_IRQHandler               ; OctoSPI2 global interrupt
+                DCD     TSC_IRQHandler                    ; Touch Sense Controller global interrupt
+                DCD     0                                 ; Reserved
+                DCD     AES_IRQHandler                    ; AES global interrupt
+                DCD     RNG_IRQHandler                    ; RNG global interrupt
+                DCD     FPU_IRQHandler                    ; FPU
+                DCD     HASH_CRS_IRQHandler               ; HASH and CRS global interrupt
+                DCD     I2C4_ER_IRQHandler                ; I2C4 error
+                DCD     I2C4_EV_IRQHandler                ; I2C4 event
+                DCD     DCMI_IRQHandler                   ; DCMI global interrupt
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     DMA2D_IRQHandler                  ; DMA2D global interrupt
+                DCD     LTDC_IRQHandler                   ; LTDC global interrupt
+                DCD     LTDC_ER_IRQHandler                ; LTDC error global interrupt
+                DCD     GFXMMU_IRQHandler                 ; GFXMMU global interrupt
+                DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX1 overrun global interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+        EXPORT     WWDG_IRQHandler                   [WEAK]
+        EXPORT     PVD_PVM_IRQHandler                [WEAK]
+        EXPORT     TAMP_STAMP_IRQHandler             [WEAK]
+        EXPORT     RTC_WKUP_IRQHandler               [WEAK]
+        EXPORT     FLASH_IRQHandler                  [WEAK]
+        EXPORT     RCC_IRQHandler                    [WEAK]
+        EXPORT     EXTI0_IRQHandler                  [WEAK]
+        EXPORT     EXTI1_IRQHandler                  [WEAK]
+        EXPORT     EXTI2_IRQHandler                  [WEAK]
+        EXPORT     EXTI3_IRQHandler                  [WEAK]
+        EXPORT     EXTI4_IRQHandler                  [WEAK]
+        EXPORT     DMA1_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel5_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel7_IRQHandler          [WEAK]
+        EXPORT     ADC1_IRQHandler                   [WEAK]
+        EXPORT     CAN1_TX_IRQHandler                [WEAK]
+        EXPORT     CAN1_RX0_IRQHandler               [WEAK]
+        EXPORT     CAN1_RX1_IRQHandler               [WEAK]
+        EXPORT     CAN1_SCE_IRQHandler               [WEAK]
+        EXPORT     EXTI9_5_IRQHandler                [WEAK]
+        EXPORT     TIM1_BRK_TIM15_IRQHandler         [WEAK]
+        EXPORT     TIM1_UP_TIM16_IRQHandler          [WEAK]
+        EXPORT     TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+        EXPORT     TIM1_CC_IRQHandler                [WEAK]
+        EXPORT     TIM2_IRQHandler                   [WEAK]
+        EXPORT     TIM3_IRQHandler                   [WEAK]
+        EXPORT     TIM4_IRQHandler                   [WEAK]
+        EXPORT     I2C1_EV_IRQHandler                [WEAK]
+        EXPORT     I2C1_ER_IRQHandler                [WEAK]
+        EXPORT     I2C2_EV_IRQHandler                [WEAK]
+        EXPORT     I2C2_ER_IRQHandler                [WEAK]
+        EXPORT     SPI1_IRQHandler                   [WEAK]
+        EXPORT     SPI2_IRQHandler                   [WEAK]
+        EXPORT     USART1_IRQHandler                 [WEAK]
+        EXPORT     USART2_IRQHandler                 [WEAK]
+        EXPORT     USART3_IRQHandler                 [WEAK]
+        EXPORT     EXTI15_10_IRQHandler              [WEAK]
+        EXPORT     RTC_Alarm_IRQHandler              [WEAK]
+        EXPORT     DFSDM1_FLT3_IRQHandler            [WEAK]
+        EXPORT     TIM8_BRK_IRQHandler               [WEAK]
+        EXPORT     TIM8_UP_IRQHandler                [WEAK]
+        EXPORT     TIM8_TRG_COM_IRQHandler           [WEAK]
+        EXPORT     TIM8_CC_IRQHandler                [WEAK]
+        EXPORT     FMC_IRQHandler                    [WEAK]
+        EXPORT     SDMMC1_IRQHandler                 [WEAK]
+        EXPORT     TIM5_IRQHandler                   [WEAK]
+        EXPORT     SPI3_IRQHandler                   [WEAK]
+        EXPORT     UART4_IRQHandler                  [WEAK]
+        EXPORT     UART5_IRQHandler                  [WEAK]
+        EXPORT     TIM6_DAC_IRQHandler               [WEAK]
+        EXPORT     TIM7_IRQHandler                   [WEAK]
+        EXPORT     DMA2_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel5_IRQHandler          [WEAK]
+        EXPORT     DFSDM1_FLT0_IRQHandler            [WEAK]
+        EXPORT     DFSDM1_FLT1_IRQHandler            [WEAK]
+        EXPORT     DFSDM1_FLT2_IRQHandler            [WEAK]
+        EXPORT     COMP_IRQHandler                   [WEAK]
+        EXPORT     LPTIM1_IRQHandler                 [WEAK]
+        EXPORT     LPTIM2_IRQHandler                 [WEAK]
+        EXPORT     OTG_FS_IRQHandler                 [WEAK]
+        EXPORT     DMA2_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel7_IRQHandler          [WEAK]
+        EXPORT     LPUART1_IRQHandler                [WEAK]
+        EXPORT     OCTOSPI1_IRQHandler               [WEAK]
+        EXPORT     I2C3_EV_IRQHandler                [WEAK]
+        EXPORT     I2C3_ER_IRQHandler                [WEAK]
+        EXPORT     SAI1_IRQHandler                   [WEAK]
+        EXPORT     SAI2_IRQHandler                   [WEAK]
+        EXPORT     OCTOSPI2_IRQHandler               [WEAK]
+        EXPORT     TSC_IRQHandler                    [WEAK]
+        EXPORT     AES_IRQHandler                    [WEAK]
+        EXPORT     RNG_IRQHandler                    [WEAK]
+        EXPORT     FPU_IRQHandler                    [WEAK]
+        EXPORT     HASH_CRS_IRQHandler               [WEAK]
+        EXPORT     I2C4_ER_IRQHandler                [WEAK]
+        EXPORT     I2C4_EV_IRQHandler                [WEAK]
+        EXPORT     DCMI_IRQHandler                   [WEAK]
+        EXPORT     DMA2D_IRQHandler                  [WEAK]
+        EXPORT     LTDC_IRQHandler                   [WEAK]
+        EXPORT     LTDC_ER_IRQHandler                [WEAK]
+        EXPORT     GFXMMU_IRQHandler                 [WEAK]
+        EXPORT     DMAMUX1_OVR_IRQHandler             [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+CAN1_TX_IRQHandler
+CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM15_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+DFSDM1_FLT3_IRQHandler
+TIM8_BRK_IRQHandler
+TIM8_UP_IRQHandler
+TIM8_TRG_COM_IRQHandler
+TIM8_CC_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+COMP_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+OTG_FS_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+LPUART1_IRQHandler
+OCTOSPI1_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SAI1_IRQHandler
+SAI2_IRQHandler
+OCTOSPI2_IRQHandler
+TSC_IRQHandler
+AES_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+HASH_CRS_IRQHandler
+I2C4_ER_IRQHandler
+I2C4_EV_IRQHandler
+DCMI_IRQHandler
+DMA2D_IRQHandler
+LTDC_IRQHandler
+LTDC_ER_IRQHandler
+GFXMMU_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

CMSIS/STM32L4xx/Source/Templates/arm/startup_stm32l4s7xx.s

@@ -0,0 +1,451 @@
+;*******************************************************************************
+;* File Name          : startup_stm32l4s7xx.s
+;* Author             : MCD Application Team
+;* Description        : STM32L4S7xx Ultra Low Power devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;*
+;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
+;*
+;*******************************************************************************
+;* <<< Use Configuration Wizard in Context Menu >>>
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x400;
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x200;
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog
+                DCD     PVD_PVM_IRQHandler                ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+                DCD     FLASH_IRQHandler                  ; FLASH
+                DCD     RCC_IRQHandler                    ; RCC
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4
+                DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7
+                DCD     ADC1_IRQHandler                   ; ADC1
+                DCD     CAN1_TX_IRQHandler                ; CAN1 TX
+                DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0
+                DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1
+                DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+                DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15
+                DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16
+                DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Commutation and TIM17
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler                   ; TIM2
+                DCD     TIM3_IRQHandler                   ; TIM3
+                DCD     TIM4_IRQHandler                   ; TIM4
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+                DCD     SPI1_IRQHandler                   ; SPI1
+                DCD     SPI2_IRQHandler                   ; SPI2
+                DCD     USART1_IRQHandler                 ; USART1
+                DCD     USART2_IRQHandler                 ; USART2
+                DCD     USART3_IRQHandler                 ; USART3
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+                DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM1 Filter 3 global Interrupt
+                DCD     TIM8_BRK_IRQHandler               ; TIM8 Break Interrupt
+                DCD     TIM8_UP_IRQHandler                ; TIM8 Update Interrupt
+                DCD     TIM8_TRG_COM_IRQHandler           ; TIM8 Trigger and Commutation Interrupt
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt
+                DCD     0                                 ; Reserved
+                DCD     FMC_IRQHandler                    ; FMC
+                DCD     SDMMC1_IRQHandler                 ; SDMMC1
+                DCD     TIM5_IRQHandler                   ; TIM5
+                DCD     SPI3_IRQHandler                   ; SPI3
+                DCD     UART4_IRQHandler                  ; UART4
+                DCD     UART5_IRQHandler                  ; UART5
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+                DCD     TIM7_IRQHandler                   ; TIM7
+                DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1
+                DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2
+                DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3
+                DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4
+                DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5
+                DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM1 Filter 0 global Interrupt
+                DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM1 Filter 1 global Interrupt
+                DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM1 Filter 2 global Interrupt
+                DCD     COMP_IRQHandler                   ; COMP Interrupt
+                DCD     LPTIM1_IRQHandler                 ; LP TIM1 interrupt
+                DCD     LPTIM2_IRQHandler                 ; LP TIM2 interrupt
+                DCD     OTG_FS_IRQHandler                 ; USB OTG FS
+                DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6
+                DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7
+                DCD     LPUART1_IRQHandler                ; LP UART1 interrupt
+                DCD     OCTOSPI1_IRQHandler               ; OctoSPI1 global interrupt
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error
+                DCD     SAI1_IRQHandler                   ; Serial Audio Interface 1 global interrupt
+                DCD     SAI2_IRQHandler                   ; Serial Audio Interface 2 global interrupt
+                DCD     OCTOSPI2_IRQHandler               ; OctoSPI2 global interrupt
+                DCD     TSC_IRQHandler                    ; Touch Sense Controller global interrupt
+                DCD     0                                 ; Reserved
+                DCD     AES_IRQHandler                    ; AES global interrupt
+                DCD     RNG_IRQHandler                    ; RNG global interrupt
+                DCD     FPU_IRQHandler                    ; FPU
+                DCD     HASH_CRS_IRQHandler               ; HASH and CRS global interrupt
+                DCD     I2C4_ER_IRQHandler                ; I2C4 error
+                DCD     I2C4_EV_IRQHandler                ; I2C4 event
+                DCD     DCMI_IRQHandler                   ; DCMI global interrupt
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     DMA2D_IRQHandler                  ; DMA2D global interrupt
+                DCD     LTDC_IRQHandler                   ; LTDC global interrupt
+                DCD     LTDC_ER_IRQHandler                ; LTDC error global interrupt
+                DCD     GFXMMU_IRQHandler                 ; GFXMMU global interrupt
+                DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX1 overrun global interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+        EXPORT     WWDG_IRQHandler                   [WEAK]
+        EXPORT     PVD_PVM_IRQHandler                [WEAK]
+        EXPORT     TAMP_STAMP_IRQHandler             [WEAK]
+        EXPORT     RTC_WKUP_IRQHandler               [WEAK]
+        EXPORT     FLASH_IRQHandler                  [WEAK]
+        EXPORT     RCC_IRQHandler                    [WEAK]
+        EXPORT     EXTI0_IRQHandler                  [WEAK]
+        EXPORT     EXTI1_IRQHandler                  [WEAK]
+        EXPORT     EXTI2_IRQHandler                  [WEAK]
+        EXPORT     EXTI3_IRQHandler                  [WEAK]
+        EXPORT     EXTI4_IRQHandler                  [WEAK]
+        EXPORT     DMA1_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel5_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel7_IRQHandler          [WEAK]
+        EXPORT     ADC1_IRQHandler                   [WEAK]
+        EXPORT     CAN1_TX_IRQHandler                [WEAK]
+        EXPORT     CAN1_RX0_IRQHandler               [WEAK]
+        EXPORT     CAN1_RX1_IRQHandler               [WEAK]
+        EXPORT     CAN1_SCE_IRQHandler               [WEAK]
+        EXPORT     EXTI9_5_IRQHandler                [WEAK]
+        EXPORT     TIM1_BRK_TIM15_IRQHandler         [WEAK]
+        EXPORT     TIM1_UP_TIM16_IRQHandler          [WEAK]
+        EXPORT     TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+        EXPORT     TIM1_CC_IRQHandler                [WEAK]
+        EXPORT     TIM2_IRQHandler                   [WEAK]
+        EXPORT     TIM3_IRQHandler                   [WEAK]
+        EXPORT     TIM4_IRQHandler                   [WEAK]
+        EXPORT     I2C1_EV_IRQHandler                [WEAK]
+        EXPORT     I2C1_ER_IRQHandler                [WEAK]
+        EXPORT     I2C2_EV_IRQHandler                [WEAK]
+        EXPORT     I2C2_ER_IRQHandler                [WEAK]
+        EXPORT     SPI1_IRQHandler                   [WEAK]
+        EXPORT     SPI2_IRQHandler                   [WEAK]
+        EXPORT     USART1_IRQHandler                 [WEAK]
+        EXPORT     USART2_IRQHandler                 [WEAK]
+        EXPORT     USART3_IRQHandler                 [WEAK]
+        EXPORT     EXTI15_10_IRQHandler              [WEAK]
+        EXPORT     RTC_Alarm_IRQHandler              [WEAK]
+        EXPORT     DFSDM1_FLT3_IRQHandler            [WEAK]
+        EXPORT     TIM8_BRK_IRQHandler               [WEAK]
+        EXPORT     TIM8_UP_IRQHandler                [WEAK]
+        EXPORT     TIM8_TRG_COM_IRQHandler           [WEAK]
+        EXPORT     TIM8_CC_IRQHandler                [WEAK]
+        EXPORT     FMC_IRQHandler                    [WEAK]
+        EXPORT     SDMMC1_IRQHandler                 [WEAK]
+        EXPORT     TIM5_IRQHandler                   [WEAK]
+        EXPORT     SPI3_IRQHandler                   [WEAK]
+        EXPORT     UART4_IRQHandler                  [WEAK]
+        EXPORT     UART5_IRQHandler                  [WEAK]
+        EXPORT     TIM6_DAC_IRQHandler               [WEAK]
+        EXPORT     TIM7_IRQHandler                   [WEAK]
+        EXPORT     DMA2_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel5_IRQHandler          [WEAK]
+        EXPORT     DFSDM1_FLT0_IRQHandler            [WEAK]
+        EXPORT     DFSDM1_FLT1_IRQHandler            [WEAK]
+        EXPORT     DFSDM1_FLT2_IRQHandler            [WEAK]
+        EXPORT     COMP_IRQHandler                   [WEAK]
+        EXPORT     LPTIM1_IRQHandler                 [WEAK]
+        EXPORT     LPTIM2_IRQHandler                 [WEAK]
+        EXPORT     OTG_FS_IRQHandler                 [WEAK]
+        EXPORT     DMA2_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel7_IRQHandler          [WEAK]
+        EXPORT     LPUART1_IRQHandler                [WEAK]
+        EXPORT     OCTOSPI1_IRQHandler               [WEAK]
+        EXPORT     I2C3_EV_IRQHandler                [WEAK]
+        EXPORT     I2C3_ER_IRQHandler                [WEAK]
+        EXPORT     SAI1_IRQHandler                   [WEAK]
+        EXPORT     SAI2_IRQHandler                   [WEAK]
+        EXPORT     OCTOSPI2_IRQHandler               [WEAK]
+        EXPORT     TSC_IRQHandler                    [WEAK]
+        EXPORT     AES_IRQHandler                    [WEAK]
+        EXPORT     RNG_IRQHandler                    [WEAK]
+        EXPORT     FPU_IRQHandler                    [WEAK]
+        EXPORT     HASH_CRS_IRQHandler               [WEAK]
+        EXPORT     I2C4_ER_IRQHandler                [WEAK]
+        EXPORT     I2C4_EV_IRQHandler                [WEAK]
+        EXPORT     DCMI_IRQHandler                   [WEAK]
+        EXPORT     DMA2D_IRQHandler                  [WEAK]
+        EXPORT     LTDC_IRQHandler                   [WEAK]
+        EXPORT     LTDC_ER_IRQHandler                [WEAK]
+        EXPORT     GFXMMU_IRQHandler                 [WEAK]
+        EXPORT     DMAMUX1_OVR_IRQHandler             [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+CAN1_TX_IRQHandler
+CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM15_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+DFSDM1_FLT3_IRQHandler
+TIM8_BRK_IRQHandler
+TIM8_UP_IRQHandler
+TIM8_TRG_COM_IRQHandler
+TIM8_CC_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+COMP_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+OTG_FS_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+LPUART1_IRQHandler
+OCTOSPI1_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SAI1_IRQHandler
+SAI2_IRQHandler
+OCTOSPI2_IRQHandler
+TSC_IRQHandler
+AES_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+HASH_CRS_IRQHandler
+I2C4_ER_IRQHandler
+I2C4_EV_IRQHandler
+DCMI_IRQHandler
+DMA2D_IRQHandler
+LTDC_IRQHandler
+LTDC_ER_IRQHandler
+GFXMMU_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

CMSIS/STM32L4xx/Source/Templates/arm/startup_stm32l4s9xx.s

@@ -0,0 +1,453 @@
+;*******************************************************************************
+;* File Name          : startup_stm32l4s9xx.s
+;* Author             : MCD Application Team
+;* Description        : STM32L4S9xx Ultra Low Power devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;*
+;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
+;*
+;*******************************************************************************
+;* <<< Use Configuration Wizard in Context Menu >>>
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x400;
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x200;
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog
+                DCD     PVD_PVM_IRQHandler                ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+                DCD     FLASH_IRQHandler                  ; FLASH
+                DCD     RCC_IRQHandler                    ; RCC
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4
+                DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7
+                DCD     ADC1_IRQHandler                   ; ADC1
+                DCD     CAN1_TX_IRQHandler                ; CAN1 TX
+                DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0
+                DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1
+                DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+                DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15
+                DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16
+                DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Commutation and TIM17
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler                   ; TIM2
+                DCD     TIM3_IRQHandler                   ; TIM3
+                DCD     TIM4_IRQHandler                   ; TIM4
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+                DCD     SPI1_IRQHandler                   ; SPI1
+                DCD     SPI2_IRQHandler                   ; SPI2
+                DCD     USART1_IRQHandler                 ; USART1
+                DCD     USART2_IRQHandler                 ; USART2
+                DCD     USART3_IRQHandler                 ; USART3
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+                DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM1 Filter 3 global Interrupt
+                DCD     TIM8_BRK_IRQHandler               ; TIM8 Break Interrupt
+                DCD     TIM8_UP_IRQHandler                ; TIM8 Update Interrupt
+                DCD     TIM8_TRG_COM_IRQHandler           ; TIM8 Trigger and Commutation Interrupt
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt
+                DCD     0                                 ; Reserved
+                DCD     FMC_IRQHandler                    ; FMC
+                DCD     SDMMC1_IRQHandler                 ; SDMMC1
+                DCD     TIM5_IRQHandler                   ; TIM5
+                DCD     SPI3_IRQHandler                   ; SPI3
+                DCD     UART4_IRQHandler                  ; UART4
+                DCD     UART5_IRQHandler                  ; UART5
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+                DCD     TIM7_IRQHandler                   ; TIM7
+                DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1
+                DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2
+                DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3
+                DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4
+                DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5
+                DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM1 Filter 0 global Interrupt
+                DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM1 Filter 1 global Interrupt
+                DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM1 Filter 2 global Interrupt
+                DCD     COMP_IRQHandler                   ; COMP Interrupt
+                DCD     LPTIM1_IRQHandler                 ; LP TIM1 interrupt
+                DCD     LPTIM2_IRQHandler                 ; LP TIM2 interrupt
+                DCD     OTG_FS_IRQHandler                 ; USB OTG FS
+                DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6
+                DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7
+                DCD     LPUART1_IRQHandler                ; LP UART1 interrupt
+                DCD     OCTOSPI1_IRQHandler               ; OctoSPI1 global interrupt
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error
+                DCD     SAI1_IRQHandler                   ; Serial Audio Interface 1 global interrupt
+                DCD     SAI2_IRQHandler                   ; Serial Audio Interface 2 global interrupt
+                DCD     OCTOSPI2_IRQHandler               ; OctoSPI2 global interrupt
+                DCD     TSC_IRQHandler                    ; Touch Sense Controller global interrupt
+                DCD     DSI_IRQHandler                    ; DSI global interrupt
+                DCD     AES_IRQHandler                    ; AES global interrupt
+                DCD     RNG_IRQHandler                    ; RNG global interrupt
+                DCD     FPU_IRQHandler                    ; FPU
+                DCD     HASH_CRS_IRQHandler               ; HASH and CRS global interrupt
+                DCD     I2C4_ER_IRQHandler                ; I2C4 error
+                DCD     I2C4_EV_IRQHandler                ; I2C4 event
+                DCD     DCMI_IRQHandler                   ; DCMI global interrupt
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     DMA2D_IRQHandler                  ; DMA2D global interrupt
+                DCD     LTDC_IRQHandler                   ; LTDC global interrupt
+                DCD     LTDC_ER_IRQHandler                ; LTDC error global interrupt
+                DCD     GFXMMU_IRQHandler                 ; GFXMMU global interrupt
+                DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX1 overrun global interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+        EXPORT     WWDG_IRQHandler                   [WEAK]
+        EXPORT     PVD_PVM_IRQHandler                [WEAK]
+        EXPORT     TAMP_STAMP_IRQHandler             [WEAK]
+        EXPORT     RTC_WKUP_IRQHandler               [WEAK]
+        EXPORT     FLASH_IRQHandler                  [WEAK]
+        EXPORT     RCC_IRQHandler                    [WEAK]
+        EXPORT     EXTI0_IRQHandler                  [WEAK]
+        EXPORT     EXTI1_IRQHandler                  [WEAK]
+        EXPORT     EXTI2_IRQHandler                  [WEAK]
+        EXPORT     EXTI3_IRQHandler                  [WEAK]
+        EXPORT     EXTI4_IRQHandler                  [WEAK]
+        EXPORT     DMA1_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel5_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel7_IRQHandler          [WEAK]
+        EXPORT     ADC1_IRQHandler                   [WEAK]
+        EXPORT     CAN1_TX_IRQHandler                [WEAK]
+        EXPORT     CAN1_RX0_IRQHandler               [WEAK]
+        EXPORT     CAN1_RX1_IRQHandler               [WEAK]
+        EXPORT     CAN1_SCE_IRQHandler               [WEAK]
+        EXPORT     EXTI9_5_IRQHandler                [WEAK]
+        EXPORT     TIM1_BRK_TIM15_IRQHandler         [WEAK]
+        EXPORT     TIM1_UP_TIM16_IRQHandler          [WEAK]
+        EXPORT     TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+        EXPORT     TIM1_CC_IRQHandler                [WEAK]
+        EXPORT     TIM2_IRQHandler                   [WEAK]
+        EXPORT     TIM3_IRQHandler                   [WEAK]
+        EXPORT     TIM4_IRQHandler                   [WEAK]
+        EXPORT     I2C1_EV_IRQHandler                [WEAK]
+        EXPORT     I2C1_ER_IRQHandler                [WEAK]
+        EXPORT     I2C2_EV_IRQHandler                [WEAK]
+        EXPORT     I2C2_ER_IRQHandler                [WEAK]
+        EXPORT     SPI1_IRQHandler                   [WEAK]
+        EXPORT     SPI2_IRQHandler                   [WEAK]
+        EXPORT     USART1_IRQHandler                 [WEAK]
+        EXPORT     USART2_IRQHandler                 [WEAK]
+        EXPORT     USART3_IRQHandler                 [WEAK]
+        EXPORT     EXTI15_10_IRQHandler              [WEAK]
+        EXPORT     RTC_Alarm_IRQHandler              [WEAK]
+        EXPORT     DFSDM1_FLT3_IRQHandler            [WEAK]
+        EXPORT     TIM8_BRK_IRQHandler               [WEAK]
+        EXPORT     TIM8_UP_IRQHandler                [WEAK]
+        EXPORT     TIM8_TRG_COM_IRQHandler           [WEAK]
+        EXPORT     TIM8_CC_IRQHandler                [WEAK]
+        EXPORT     FMC_IRQHandler                    [WEAK]
+        EXPORT     SDMMC1_IRQHandler                 [WEAK]
+        EXPORT     TIM5_IRQHandler                   [WEAK]
+        EXPORT     SPI3_IRQHandler                   [WEAK]
+        EXPORT     UART4_IRQHandler                  [WEAK]
+        EXPORT     UART5_IRQHandler                  [WEAK]
+        EXPORT     TIM6_DAC_IRQHandler               [WEAK]
+        EXPORT     TIM7_IRQHandler                   [WEAK]
+        EXPORT     DMA2_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel5_IRQHandler          [WEAK]
+        EXPORT     DFSDM1_FLT0_IRQHandler            [WEAK]
+        EXPORT     DFSDM1_FLT1_IRQHandler            [WEAK]
+        EXPORT     DFSDM1_FLT2_IRQHandler            [WEAK]
+        EXPORT     COMP_IRQHandler                   [WEAK]
+        EXPORT     LPTIM1_IRQHandler                 [WEAK]
+        EXPORT     LPTIM2_IRQHandler                 [WEAK]
+        EXPORT     OTG_FS_IRQHandler                 [WEAK]
+        EXPORT     DMA2_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel7_IRQHandler          [WEAK]
+        EXPORT     LPUART1_IRQHandler                [WEAK]
+        EXPORT     OCTOSPI1_IRQHandler               [WEAK]
+        EXPORT     I2C3_EV_IRQHandler                [WEAK]
+        EXPORT     I2C3_ER_IRQHandler                [WEAK]
+        EXPORT     SAI1_IRQHandler                   [WEAK]
+        EXPORT     SAI2_IRQHandler                   [WEAK]
+        EXPORT     OCTOSPI2_IRQHandler               [WEAK]
+        EXPORT     TSC_IRQHandler                    [WEAK]
+        EXPORT     DSI_IRQHandler                    [WEAK]
+        EXPORT     AES_IRQHandler                    [WEAK]
+        EXPORT     RNG_IRQHandler                    [WEAK]
+        EXPORT     FPU_IRQHandler                    [WEAK]
+        EXPORT     HASH_CRS_IRQHandler               [WEAK]
+        EXPORT     I2C4_ER_IRQHandler                [WEAK]
+        EXPORT     I2C4_EV_IRQHandler                [WEAK]
+        EXPORT     DCMI_IRQHandler                   [WEAK]
+        EXPORT     DMA2D_IRQHandler                  [WEAK]
+        EXPORT     LTDC_IRQHandler                   [WEAK]
+        EXPORT     LTDC_ER_IRQHandler                [WEAK]
+        EXPORT     GFXMMU_IRQHandler                 [WEAK]
+        EXPORT     DMAMUX1_OVR_IRQHandler             [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+CAN1_TX_IRQHandler
+CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM15_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+DFSDM1_FLT3_IRQHandler
+TIM8_BRK_IRQHandler
+TIM8_UP_IRQHandler
+TIM8_TRG_COM_IRQHandler
+TIM8_CC_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+COMP_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+OTG_FS_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+LPUART1_IRQHandler
+OCTOSPI1_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SAI1_IRQHandler
+SAI2_IRQHandler
+OCTOSPI2_IRQHandler
+TSC_IRQHandler
+DSI_IRQHandler
+AES_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+HASH_CRS_IRQHandler
+I2C4_ER_IRQHandler
+I2C4_EV_IRQHandler
+DCMI_IRQHandler
+DMA2D_IRQHandler
+LTDC_IRQHandler
+LTDC_ER_IRQHandler
+GFXMMU_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

CMSIS/STM32L4xx/Source/Templates/gcc/startup_stm32l412xx.s

@@ -0,0 +1,435 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32l412xx.s
+  * @author    MCD Application Team
+  * @brief     STM32L412xx devices vector table for GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address,
+  *                - Configure the clock system
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Apache License, Version 2.0,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/Apache-2.0
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+    .cpu cortex-m4
+    .fpu softvfp
+    .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word   _sidata
+/* start address for the .data section. defined in linker script */
+.word   _sdata
+/* end address for the .data section. defined in linker script */
+.word   _edata
+/* start address for the .bss section. defined in linker script */
+.word   _sbss
+/* end address for the .bss section. defined in linker script */
+.word   _ebss
+
+.equ  BootRAM,        0xF1E0F85F
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+    .section    .text.Reset_Handler
+    .weak   Reset_Handler
+    .type   Reset_Handler, %function
+Reset_Handler:
+  ldr   sp, =_estack    /* Set stack pointer */
+
+/* Call the clock system initialization function.*/
+    bl  SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b LoopCopyDataInit
+
+CopyDataInit:
+    ldr r3, =_sidata
+    ldr r3, [r3, r1]
+    str r3, [r0, r1]
+    adds    r1, r1, #4
+
+LoopCopyDataInit:
+    ldr r0, =_sdata
+    ldr r3, =_edata
+    adds    r2, r0, r1
+    cmp r2, r3
+    bcc CopyDataInit
+    ldr r2, =_sbss
+    b   LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+    movs    r3, #0
+    str r3, [r2], #4
+
+LoopFillZerobss:
+    ldr r3, = _ebss
+    cmp r2, r3
+    bcc FillZerobss
+
+/* Call static constructors */
+    bl __libc_init_array
+/* Call the application's entry point.*/
+    bl  main
+
+LoopForever:
+    b LoopForever
+
+.size   Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section    .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+    b   Infinite_Loop
+    .size   Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+    .section    .isr_vector,"a",%progbits
+    .type   g_pfnVectors, %object
+    .size   g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+    .word   _estack
+    .word   Reset_Handler
+    .word   NMI_Handler
+    .word   HardFault_Handler
+    .word   MemManage_Handler
+    .word   BusFault_Handler
+    .word   UsageFault_Handler
+    .word   0
+    .word   0
+    .word   0
+    .word   0
+    .word   SVC_Handler
+    .word   DebugMon_Handler
+    .word   0
+    .word   PendSV_Handler
+    .word   SysTick_Handler
+    .word   WWDG_IRQHandler
+    .word   PVD_PVM_IRQHandler
+    .word   TAMP_STAMP_IRQHandler
+    .word   RTC_WKUP_IRQHandler
+    .word   FLASH_IRQHandler
+    .word   RCC_IRQHandler
+    .word   EXTI0_IRQHandler
+    .word   EXTI1_IRQHandler
+    .word   EXTI2_IRQHandler
+    .word   EXTI3_IRQHandler
+    .word   EXTI4_IRQHandler
+    .word   DMA1_Channel1_IRQHandler
+    .word   DMA1_Channel2_IRQHandler
+    .word   DMA1_Channel3_IRQHandler
+    .word   DMA1_Channel4_IRQHandler
+    .word   DMA1_Channel5_IRQHandler
+    .word   DMA1_Channel6_IRQHandler
+    .word   DMA1_Channel7_IRQHandler
+    .word   ADC1_2_IRQHandler
+    .word   0
+    .word   0
+    .word   0
+    .word   0
+    .word   EXTI9_5_IRQHandler
+    .word   TIM1_BRK_TIM15_IRQHandler
+    .word   TIM1_UP_TIM16_IRQHandler
+    .word   TIM1_TRG_COM_IRQHandler
+    .word   TIM1_CC_IRQHandler
+    .word   TIM2_IRQHandler
+    .word   0
+    .word   0
+    .word   I2C1_EV_IRQHandler
+    .word   I2C1_ER_IRQHandler
+    .word   I2C2_EV_IRQHandler
+    .word   I2C2_ER_IRQHandler
+    .word   SPI1_IRQHandler
+    .word   SPI2_IRQHandler
+    .word   USART1_IRQHandler
+    .word   USART2_IRQHandler
+    .word   USART3_IRQHandler
+    .word   EXTI15_10_IRQHandler
+    .word   RTC_Alarm_IRQHandler
+    .word   0
+    .word   0
+    .word   0
+    .word   0
+    .word   0
+    .word   0
+    .word   0
+    .word   0
+    .word   0
+    .word   0
+    .word   0
+    .word   0
+    .word   TIM6_IRQHandler
+    .word   0
+    .word   DMA2_Channel1_IRQHandler
+    .word   DMA2_Channel2_IRQHandler
+    .word   DMA2_Channel3_IRQHandler
+    .word   DMA2_Channel4_IRQHandler
+    .word   DMA2_Channel5_IRQHandler
+    .word   0
+    .word   0
+    .word   0
+    .word   COMP_IRQHandler
+    .word   LPTIM1_IRQHandler
+    .word   LPTIM2_IRQHandler
+    .word   USB_IRQHandler
+    .word   DMA2_Channel6_IRQHandler
+    .word   DMA2_Channel7_IRQHandler
+    .word   LPUART1_IRQHandler
+    .word   QUADSPI_IRQHandler
+    .word   I2C3_EV_IRQHandler
+    .word   I2C3_ER_IRQHandler
+    .word   0
+    .word   0
+    .word   0
+    .word   TSC_IRQHandler
+    .word   0
+    .word   0
+    .word   RNG_IRQHandler
+    .word   FPU_IRQHandler
+    .word   CRS_IRQHandler
+
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+  .weak NMI_Handler
+    .thumb_set NMI_Handler,Default_Handler
+
+  .weak HardFault_Handler
+    .thumb_set HardFault_Handler,Default_Handler
+
+  .weak MemManage_Handler
+    .thumb_set MemManage_Handler,Default_Handler
+
+  .weak BusFault_Handler
+    .thumb_set BusFault_Handler,Default_Handler
+
+    .weak   UsageFault_Handler
+    .thumb_set UsageFault_Handler,Default_Handler
+
+    .weak   SVC_Handler
+    .thumb_set SVC_Handler,Default_Handler
+
+    .weak   DebugMon_Handler
+    .thumb_set DebugMon_Handler,Default_Handler
+
+    .weak   PendSV_Handler
+    .thumb_set PendSV_Handler,Default_Handler
+
+    .weak   SysTick_Handler
+    .thumb_set SysTick_Handler,Default_Handler
+
+    .weak   WWDG_IRQHandler
+    .thumb_set WWDG_IRQHandler,Default_Handler
+
+    .weak   PVD_PVM_IRQHandler
+    .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+    .weak   TAMP_STAMP_IRQHandler
+    .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+    .weak   RTC_WKUP_IRQHandler
+    .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+    .weak   FLASH_IRQHandler
+    .thumb_set FLASH_IRQHandler,Default_Handler
+
+    .weak   RCC_IRQHandler
+    .thumb_set RCC_IRQHandler,Default_Handler
+
+    .weak   EXTI0_IRQHandler
+    .thumb_set EXTI0_IRQHandler,Default_Handler
+
+    .weak   EXTI1_IRQHandler
+    .thumb_set EXTI1_IRQHandler,Default_Handler
+
+    .weak   EXTI2_IRQHandler
+    .thumb_set EXTI2_IRQHandler,Default_Handler
+
+    .weak   EXTI3_IRQHandler
+    .thumb_set EXTI3_IRQHandler,Default_Handler
+
+    .weak   EXTI4_IRQHandler
+    .thumb_set EXTI4_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel1_IRQHandler
+    .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel2_IRQHandler
+    .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel3_IRQHandler
+    .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel4_IRQHandler
+    .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel5_IRQHandler
+    .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel6_IRQHandler
+    .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel7_IRQHandler
+    .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+    .weak   ADC1_2_IRQHandler
+    .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+    .weak   EXTI9_5_IRQHandler
+    .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+    .weak   TIM1_BRK_TIM15_IRQHandler
+    .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+    .weak   TIM1_UP_TIM16_IRQHandler
+    .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+    .weak   TIM1_TRG_COM_IRQHandler
+    .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+    .weak   TIM1_CC_IRQHandler
+    .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+    .weak   TIM2_IRQHandler
+    .thumb_set TIM2_IRQHandler,Default_Handler
+
+    .weak   I2C1_EV_IRQHandler
+    .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+    .weak   I2C1_ER_IRQHandler
+    .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+    .weak   I2C2_EV_IRQHandler
+    .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+    .weak   I2C2_ER_IRQHandler
+    .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+    .weak   SPI1_IRQHandler
+    .thumb_set SPI1_IRQHandler,Default_Handler
+
+    .weak   SPI2_IRQHandler
+    .thumb_set SPI2_IRQHandler,Default_Handler
+
+    .weak   USART1_IRQHandler
+    .thumb_set USART1_IRQHandler,Default_Handler
+
+    .weak   USART2_IRQHandler
+    .thumb_set USART2_IRQHandler,Default_Handler
+
+    .weak   USART3_IRQHandler
+    .thumb_set USART3_IRQHandler,Default_Handler
+
+    .weak   EXTI15_10_IRQHandler
+    .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+    .weak   RTC_Alarm_IRQHandler
+    .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+    .weak   TIM6_IRQHandler
+    .thumb_set TIM6_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel1_IRQHandler
+    .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel2_IRQHandler
+    .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel3_IRQHandler
+    .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel4_IRQHandler
+    .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel5_IRQHandler
+    .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+    .weak   COMP_IRQHandler
+    .thumb_set COMP_IRQHandler,Default_Handler
+
+    .weak   LPTIM1_IRQHandler
+    .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+    .weak   LPTIM2_IRQHandler
+    .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+    .weak   USB_IRQHandler
+    .thumb_set USB_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel6_IRQHandler
+    .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel7_IRQHandler
+    .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+    .weak   LPUART1_IRQHandler
+    .thumb_set LPUART1_IRQHandler,Default_Handler
+
+    .weak   QUADSPI_IRQHandler
+    .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+    .weak   I2C3_EV_IRQHandler
+    .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+    .weak   I2C3_ER_IRQHandler
+    .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+    .weak   TSC_IRQHandler
+    .thumb_set TSC_IRQHandler,Default_Handler
+
+    .weak   RNG_IRQHandler
+    .thumb_set RNG_IRQHandler,Default_Handler
+
+    .weak   FPU_IRQHandler
+    .thumb_set FPU_IRQHandler,Default_Handler
+
+    .weak   CRS_IRQHandler
+    .thumb_set CRS_IRQHandler,Default_Handler
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

CMSIS/STM32L4xx/Source/Templates/gcc/startup_stm32l422xx.s

@@ -0,0 +1,438 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32l412xx.s
+  * @author    MCD Application Team
+  * @brief     STM32L412xx devices vector table for GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address,
+  *                - Configure the clock system
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Apache License, Version 2.0,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/Apache-2.0
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+    .cpu cortex-m4
+    .fpu softvfp
+    .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word   _sidata
+/* start address for the .data section. defined in linker script */
+.word   _sdata
+/* end address for the .data section. defined in linker script */
+.word   _edata
+/* start address for the .bss section. defined in linker script */
+.word   _sbss
+/* end address for the .bss section. defined in linker script */
+.word   _ebss
+
+.equ  BootRAM,        0xF1E0F85F
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+    .section    .text.Reset_Handler
+    .weak   Reset_Handler
+    .type   Reset_Handler, %function
+Reset_Handler:
+  ldr   sp, =_estack    /* Set stack pointer */
+
+/* Call the clock system initialization function.*/
+    bl  SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b LoopCopyDataInit
+
+CopyDataInit:
+    ldr r3, =_sidata
+    ldr r3, [r3, r1]
+    str r3, [r0, r1]
+    adds    r1, r1, #4
+
+LoopCopyDataInit:
+    ldr r0, =_sdata
+    ldr r3, =_edata
+    adds    r2, r0, r1
+    cmp r2, r3
+    bcc CopyDataInit
+    ldr r2, =_sbss
+    b   LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+    movs    r3, #0
+    str r3, [r2], #4
+
+LoopFillZerobss:
+    ldr r3, = _ebss
+    cmp r2, r3
+    bcc FillZerobss
+
+/* Call static constructors */
+    bl __libc_init_array
+/* Call the application's entry point.*/
+    bl  main
+
+LoopForever:
+    b LoopForever
+
+.size   Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section    .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+    b   Infinite_Loop
+    .size   Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+    .section    .isr_vector,"a",%progbits
+    .type   g_pfnVectors, %object
+    .size   g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+    .word   _estack
+    .word   Reset_Handler
+    .word   NMI_Handler
+    .word   HardFault_Handler
+    .word   MemManage_Handler
+    .word   BusFault_Handler
+    .word   UsageFault_Handler
+    .word   0
+    .word   0
+    .word   0
+    .word   0
+    .word   SVC_Handler
+    .word   DebugMon_Handler
+    .word   0
+    .word   PendSV_Handler
+    .word   SysTick_Handler
+    .word   WWDG_IRQHandler
+    .word   PVD_PVM_IRQHandler
+    .word   TAMP_STAMP_IRQHandler
+    .word   RTC_WKUP_IRQHandler
+    .word   FLASH_IRQHandler
+    .word   RCC_IRQHandler
+    .word   EXTI0_IRQHandler
+    .word   EXTI1_IRQHandler
+    .word   EXTI2_IRQHandler
+    .word   EXTI3_IRQHandler
+    .word   EXTI4_IRQHandler
+    .word   DMA1_Channel1_IRQHandler
+    .word   DMA1_Channel2_IRQHandler
+    .word   DMA1_Channel3_IRQHandler
+    .word   DMA1_Channel4_IRQHandler
+    .word   DMA1_Channel5_IRQHandler
+    .word   DMA1_Channel6_IRQHandler
+    .word   DMA1_Channel7_IRQHandler
+    .word   ADC1_2_IRQHandler
+    .word   0
+    .word   0
+    .word   0
+    .word   0
+    .word   EXTI9_5_IRQHandler
+    .word   TIM1_BRK_TIM15_IRQHandler
+    .word   TIM1_UP_TIM16_IRQHandler
+    .word   TIM1_TRG_COM_IRQHandler
+    .word   TIM1_CC_IRQHandler
+    .word   TIM2_IRQHandler
+    .word   0
+    .word   0
+    .word   I2C1_EV_IRQHandler
+    .word   I2C1_ER_IRQHandler
+    .word   I2C2_EV_IRQHandler
+    .word   I2C2_ER_IRQHandler
+    .word   SPI1_IRQHandler
+    .word   SPI2_IRQHandler
+    .word   USART1_IRQHandler
+    .word   USART2_IRQHandler
+    .word   USART3_IRQHandler
+    .word   EXTI15_10_IRQHandler
+    .word   RTC_Alarm_IRQHandler
+    .word   0
+    .word   0
+    .word   0
+    .word   0
+    .word   0
+    .word   0
+    .word   0
+    .word   0
+    .word   0
+    .word   0
+    .word   0
+    .word   0
+    .word   TIM6_IRQHandler
+    .word   0
+    .word   DMA2_Channel1_IRQHandler
+    .word   DMA2_Channel2_IRQHandler
+    .word   DMA2_Channel3_IRQHandler
+    .word   DMA2_Channel4_IRQHandler
+    .word   DMA2_Channel5_IRQHandler
+    .word   0
+    .word   0
+    .word   0
+    .word   COMP_IRQHandler
+    .word   LPTIM1_IRQHandler
+    .word   LPTIM2_IRQHandler
+    .word   USB_IRQHandler
+    .word   DMA2_Channel6_IRQHandler
+    .word   DMA2_Channel7_IRQHandler
+    .word   LPUART1_IRQHandler
+    .word   QUADSPI_IRQHandler
+    .word   I2C3_EV_IRQHandler
+    .word   I2C3_ER_IRQHandler
+    .word   0
+    .word   0
+    .word   0
+    .word   TSC_IRQHandler
+    .word   0
+    .word   AES_IRQHandler
+    .word   RNG_IRQHandler
+    .word   FPU_IRQHandler
+    .word   CRS_IRQHandler
+
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+  .weak NMI_Handler
+    .thumb_set NMI_Handler,Default_Handler
+
+  .weak HardFault_Handler
+    .thumb_set HardFault_Handler,Default_Handler
+
+  .weak MemManage_Handler
+    .thumb_set MemManage_Handler,Default_Handler
+
+  .weak BusFault_Handler
+    .thumb_set BusFault_Handler,Default_Handler
+
+    .weak   UsageFault_Handler
+    .thumb_set UsageFault_Handler,Default_Handler
+
+    .weak   SVC_Handler
+    .thumb_set SVC_Handler,Default_Handler
+
+    .weak   DebugMon_Handler
+    .thumb_set DebugMon_Handler,Default_Handler
+
+    .weak   PendSV_Handler
+    .thumb_set PendSV_Handler,Default_Handler
+
+    .weak   SysTick_Handler
+    .thumb_set SysTick_Handler,Default_Handler
+
+    .weak   WWDG_IRQHandler
+    .thumb_set WWDG_IRQHandler,Default_Handler
+
+    .weak   PVD_PVM_IRQHandler
+    .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+    .weak   TAMP_STAMP_IRQHandler
+    .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+    .weak   RTC_WKUP_IRQHandler
+    .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+    .weak   FLASH_IRQHandler
+    .thumb_set FLASH_IRQHandler,Default_Handler
+
+    .weak   RCC_IRQHandler
+    .thumb_set RCC_IRQHandler,Default_Handler
+
+    .weak   EXTI0_IRQHandler
+    .thumb_set EXTI0_IRQHandler,Default_Handler
+
+    .weak   EXTI1_IRQHandler
+    .thumb_set EXTI1_IRQHandler,Default_Handler
+
+    .weak   EXTI2_IRQHandler
+    .thumb_set EXTI2_IRQHandler,Default_Handler
+
+    .weak   EXTI3_IRQHandler
+    .thumb_set EXTI3_IRQHandler,Default_Handler
+
+    .weak   EXTI4_IRQHandler
+    .thumb_set EXTI4_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel1_IRQHandler
+    .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel2_IRQHandler
+    .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel3_IRQHandler
+    .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel4_IRQHandler
+    .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel5_IRQHandler
+    .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel6_IRQHandler
+    .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel7_IRQHandler
+    .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+    .weak   ADC1_2_IRQHandler
+    .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+    .weak   EXTI9_5_IRQHandler
+    .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+    .weak   TIM1_BRK_TIM15_IRQHandler
+    .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+    .weak   TIM1_UP_TIM16_IRQHandler
+    .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+    .weak   TIM1_TRG_COM_IRQHandler
+    .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+    .weak   TIM1_CC_IRQHandler
+    .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+    .weak   TIM2_IRQHandler
+    .thumb_set TIM2_IRQHandler,Default_Handler
+
+    .weak   I2C1_EV_IRQHandler
+    .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+    .weak   I2C1_ER_IRQHandler
+    .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+    .weak   I2C2_EV_IRQHandler
+    .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+    .weak   I2C2_ER_IRQHandler
+    .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+    .weak   SPI1_IRQHandler
+    .thumb_set SPI1_IRQHandler,Default_Handler
+
+    .weak   SPI2_IRQHandler
+    .thumb_set SPI2_IRQHandler,Default_Handler
+
+    .weak   USART1_IRQHandler
+    .thumb_set USART1_IRQHandler,Default_Handler
+
+    .weak   USART2_IRQHandler
+    .thumb_set USART2_IRQHandler,Default_Handler
+
+    .weak   USART3_IRQHandler
+    .thumb_set USART3_IRQHandler,Default_Handler
+
+    .weak   EXTI15_10_IRQHandler
+    .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+    .weak   RTC_Alarm_IRQHandler
+    .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+    .weak   TIM6_IRQHandler
+    .thumb_set TIM6_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel1_IRQHandler
+    .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel2_IRQHandler
+    .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel3_IRQHandler
+    .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel4_IRQHandler
+    .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel5_IRQHandler
+    .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+    .weak   COMP_IRQHandler
+    .thumb_set COMP_IRQHandler,Default_Handler
+
+    .weak   LPTIM1_IRQHandler
+    .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+    .weak   LPTIM2_IRQHandler
+    .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+    .weak   USB_IRQHandler
+    .thumb_set USB_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel6_IRQHandler
+    .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel7_IRQHandler
+    .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+    .weak   LPUART1_IRQHandler
+    .thumb_set LPUART1_IRQHandler,Default_Handler
+
+    .weak   QUADSPI_IRQHandler
+    .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+    .weak   I2C3_EV_IRQHandler
+    .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+    .weak   I2C3_ER_IRQHandler
+    .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+    .weak   TSC_IRQHandler
+    .thumb_set TSC_IRQHandler,Default_Handler
+
+    .weak   AES_IRQHandler
+    .thumb_set AES_IRQHandler,Default_Handler
+
+    .weak   RNG_IRQHandler
+    .thumb_set RNG_IRQHandler,Default_Handler
+
+    .weak   FPU_IRQHandler
+    .thumb_set FPU_IRQHandler,Default_Handler
+
+    .weak   CRS_IRQHandler
+    .thumb_set CRS_IRQHandler,Default_Handler
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

CMSIS/STM32L4xx/Source/Templates/gcc/startup_stm32l431xx.s

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file      startup_stm32l431xx.s
   * @author    MCD Application Team
-  * @version   V1.3.2
-  * @date      16-June-2017
   * @brief     STM32L431xx devices vector table for GCC toolchain.
   *            This module performs:
   *                - Set the initial SP
@@ -17,29 +15,13 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under Apache License, Version 2.0,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/Apache-2.0
   *
   ******************************************************************************
   */
@@ -78,7 +60,10 @@ defined in linker script */
     .weak   Reset_Handler
     .type   Reset_Handler, %function
 Reset_Handler:
-  ldr   sp, =_estack    /* Atollic update: set stack pointer */
+  ldr   sp, =_estack    /* Set stack pointer */
+
+/* Call the clock system initialization function.*/
+    bl  SystemInit
 
 /* Copy the data segment initializers from flash to SRAM */
   movs  r1, #0
@@ -108,8 +93,6 @@ LoopFillZerobss:
     cmp r2, r3
     bcc FillZerobss
 
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
 /* Call static constructors */
     bl __libc_init_array
 /* Call the application's entry point.*/

CMSIS/STM32L4xx/Source/Templates/gcc/startup_stm32l432xx.s

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file      startup_stm32l432xx.s
   * @author    MCD Application Team
-  * @version   V1.3.2
-  * @date      16-June-2017
   * @brief     STM32L432xx devices vector table for GCC toolchain.
   *            This module performs:
   *                - Set the initial SP
@@ -17,29 +15,13 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under Apache License, Version 2.0,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/Apache-2.0
   *
   ******************************************************************************
   */
@@ -78,7 +60,10 @@ defined in linker script */
     .weak   Reset_Handler
     .type   Reset_Handler, %function
 Reset_Handler:
-  ldr   sp, =_estack    /* Atollic update: set stack pointer */
+  ldr   sp, =_estack    /* Set stack pointer */
+
+/* Call the clock system initialization function.*/
+    bl  SystemInit
 
 /* Copy the data segment initializers from flash to SRAM */
   movs  r1, #0
@@ -108,8 +93,6 @@ LoopFillZerobss:
     cmp r2, r3
     bcc FillZerobss
 
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
 /* Call static constructors */
     bl __libc_init_array
 /* Call the application's entry point.*/

CMSIS/STM32L4xx/Source/Templates/gcc/startup_stm32l433xx.s

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file      startup_stm32l433xx.s
   * @author    MCD Application Team
-  * @version   V1.3.2
-  * @date      16-June-2017
   * @brief     STM32L433xx devices vector table for GCC toolchain.
   *            This module performs:
   *                - Set the initial SP
@@ -17,29 +15,13 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under Apache License, Version 2.0,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/Apache-2.0
   *
   ******************************************************************************
   */
@@ -78,7 +60,10 @@ defined in linker script */
     .weak   Reset_Handler
     .type   Reset_Handler, %function
 Reset_Handler:
-  ldr   sp, =_estack    /* Atollic update: set stack pointer */
+  ldr   sp, =_estack    /* Set stack pointer */
+
+/* Call the clock system initialization function.*/
+    bl  SystemInit
 
 /* Copy the data segment initializers from flash to SRAM */
   movs  r1, #0
@@ -108,8 +93,6 @@ LoopFillZerobss:
     cmp r2, r3
     bcc FillZerobss
 
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
 /* Call static constructors */
     bl __libc_init_array
 /* Call the application's entry point.*/

CMSIS/STM32L4xx/Source/Templates/gcc/startup_stm32l442xx.s

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file      startup_stm32l442xx.s
   * @author    MCD Application Team
-  * @version   V1.3.2
-  * @date      16-June-2017
   * @brief     STM32L442xx devices vector table for GCC toolchain.
   *            This module performs:
   *                - Set the initial SP
@@ -17,29 +15,13 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under Apache License, Version 2.0,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/Apache-2.0
   *
   ******************************************************************************
   */
@@ -78,7 +60,10 @@ defined in linker script */
     .weak   Reset_Handler
     .type   Reset_Handler, %function
 Reset_Handler:
-  ldr   sp, =_estack    /* Atollic update: set stack pointer */
+  ldr   sp, =_estack    /* Set stack pointer */
+
+/* Call the clock system initialization function.*/
+    bl  SystemInit
 
 /* Copy the data segment initializers from flash to SRAM */
   movs  r1, #0
@@ -108,8 +93,6 @@ LoopFillZerobss:
     cmp r2, r3
     bcc FillZerobss
 
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
 /* Call static constructors */
     bl __libc_init_array
 /* Call the application's entry point.*/

CMSIS/STM32L4xx/Source/Templates/gcc/startup_stm32l443xx.s

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file      startup_stm32l443xx.s
   * @author    MCD Application Team
-  * @version   V1.3.2
-  * @date      16-June-2017
   * @brief     STM32L443xx devices vector table for GCC toolchain.
   *            This module performs:
   *                - Set the initial SP
@@ -17,29 +15,13 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under Apache License, Version 2.0,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/Apache-2.0
   *
   ******************************************************************************
   */
@@ -78,7 +60,10 @@ defined in linker script */
     .weak   Reset_Handler
     .type   Reset_Handler, %function
 Reset_Handler:
-  ldr   sp, =_estack    /* Atollic update: set stack pointer */
+  ldr   sp, =_estack    /* Set stack pointer */
+
+/* Call the clock system initialization function.*/
+    bl  SystemInit
 
 /* Copy the data segment initializers from flash to SRAM */
   movs  r1, #0
@@ -108,8 +93,6 @@ LoopFillZerobss:
     cmp r2, r3
     bcc FillZerobss
 
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
 /* Call static constructors */
     bl __libc_init_array
 /* Call the application's entry point.*/

CMSIS/STM32L4xx/Source/Templates/gcc/startup_stm32l451xx.s

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file      startup_stm32l451xx.s
   * @author    MCD Application Team
-  * @version   V1.3.2
-  * @date      16-June-2017
   * @brief     STM32L451xx devices vector table for GCC toolchain.
   *            This module performs:
   *                - Set the initial SP
@@ -17,29 +15,13 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under Apache License, Version 2.0,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/Apache-2.0
   *
   ******************************************************************************
   */
@@ -78,7 +60,10 @@ defined in linker script */
     .weak   Reset_Handler
     .type   Reset_Handler, %function
 Reset_Handler:
-  ldr   sp, =_estack    /* Atollic update: set stack pointer */
+  ldr   sp, =_estack    /* Set stack pointer */
+
+/* Call the clock system initialization function.*/
+    bl  SystemInit
 
 /* Copy the data segment initializers from flash to SRAM */
   movs  r1, #0
@@ -108,8 +93,6 @@ LoopFillZerobss:
     cmp r2, r3
     bcc FillZerobss
 
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
 /* Call static constructors */
     bl __libc_init_array
 /* Call the application's entry point.*/

CMSIS/STM32L4xx/Source/Templates/gcc/startup_stm32l452xx.s

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file      startup_stm32l452xx.s
   * @author    MCD Application Team
-  * @version   V1.3.2
-  * @date      16-June-2017
   * @brief     STM32L452xx devices vector table for GCC toolchain.
   *            This module performs:
   *                - Set the initial SP
@@ -17,29 +15,13 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under Apache License, Version 2.0,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/Apache-2.0
   *
   ******************************************************************************
   */
@@ -78,7 +60,10 @@ defined in linker script */
     .weak   Reset_Handler
     .type   Reset_Handler, %function
 Reset_Handler:
-  ldr   sp, =_estack    /* Atollic update: set stack pointer */
+  ldr   sp, =_estack    /* Set stack pointer */
+
+/* Call the clock system initialization function.*/
+    bl  SystemInit
 
 /* Copy the data segment initializers from flash to SRAM */
   movs  r1, #0
@@ -108,8 +93,6 @@ LoopFillZerobss:
     cmp r2, r3
     bcc FillZerobss
 
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
 /* Call static constructors */
     bl __libc_init_array
 /* Call the application's entry point.*/

CMSIS/STM32L4xx/Source/Templates/gcc/startup_stm32l462xx.s

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file      startup_stm32l462xx.s
   * @author    MCD Application Team
-  * @version   V1.3.2
-  * @date      16-June-2017
   * @brief     STM32L462xx devices vector table for GCC toolchain.
   *            This module performs:
   *                - Set the initial SP
@@ -17,29 +15,13 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under Apache License, Version 2.0,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/Apache-2.0
   *
   ******************************************************************************
   */
@@ -78,7 +60,10 @@ defined in linker script */
     .weak   Reset_Handler
     .type   Reset_Handler, %function
 Reset_Handler:
-  ldr   sp, =_estack    /* Atollic update: set stack pointer */
+  ldr   sp, =_estack    /* Set stack pointer */
+
+/* Call the clock system initialization function.*/
+    bl  SystemInit
 
 /* Copy the data segment initializers from flash to SRAM */
   movs  r1, #0
@@ -108,8 +93,6 @@ LoopFillZerobss:
     cmp r2, r3
     bcc FillZerobss
 
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
 /* Call static constructors */
     bl __libc_init_array
 /* Call the application's entry point.*/

CMSIS/STM32L4xx/Source/Templates/gcc/startup_stm32l471xx.s

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file      startup_stm32l471xx.s
   * @author    MCD Application Team
-  * @version   V1.3.2
-  * @date      16-June-2017
   * @brief     STM32L471xx devices vector table for GCC toolchain.
   *            This module performs:
   *                - Set the initial SP
@@ -17,29 +15,13 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under Apache License, Version 2.0,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/Apache-2.0
   *
   ******************************************************************************
   */
@@ -78,7 +60,10 @@ defined in linker script */
     .weak   Reset_Handler
     .type   Reset_Handler, %function
 Reset_Handler:
-  ldr   sp, =_estack    /* Atollic update: set stack pointer */
+  ldr   sp, =_estack    /* Set stack pointer */
+
+/* Call the clock system initialization function.*/
+    bl  SystemInit
 
 /* Copy the data segment initializers from flash to SRAM */
   movs  r1, #0
@@ -108,8 +93,6 @@ LoopFillZerobss:
     cmp r2, r3
     bcc FillZerobss
 
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
 /* Call static constructors */
     bl __libc_init_array
 /* Call the application's entry point.*/

CMSIS/STM32L4xx/Source/Templates/gcc/startup_stm32l475xx.s

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file      startup_stm32l475xx.s
   * @author    MCD Application Team
-  * @version   V1.3.2
-  * @date      16-June-2017
   * @brief     STM32L475xx devices vector table for GCC toolchain.
   *            This module performs:
   *                - Set the initial SP
@@ -17,29 +15,13 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under Apache License, Version 2.0,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/Apache-2.0
   *
   ******************************************************************************
   */
@@ -78,7 +60,10 @@ defined in linker script */
     .weak   Reset_Handler
     .type   Reset_Handler, %function
 Reset_Handler:
-  ldr   sp, =_estack    /* Atollic update: set stack pointer */
+  ldr   sp, =_estack    /* Set stack pointer */
+
+/* Call the clock system initialization function.*/
+    bl  SystemInit
 
 /* Copy the data segment initializers from flash to SRAM */
   movs  r1, #0
@@ -108,8 +93,6 @@ LoopFillZerobss:
     cmp r2, r3
     bcc FillZerobss
 
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
 /* Call static constructors */
     bl __libc_init_array
 /* Call the application's entry point.*/

CMSIS/STM32L4xx/Source/Templates/gcc/startup_stm32l476xx.s

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file      startup_stm32l476xx.s
   * @author    MCD Application Team
-  * @version   V1.3.2
-  * @date      16-June-2017
   * @brief     STM32L476xx devices vector table GCC toolchain.
   *            This module performs:
   *                - Set the initial SP
@@ -17,29 +15,13 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under Apache License, Version 2.0,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/Apache-2.0
   *
   ******************************************************************************
   */
@@ -78,7 +60,10 @@ defined in linker script */
     .weak   Reset_Handler
     .type   Reset_Handler, %function
 Reset_Handler:
-  ldr   sp, =_estack    /* Atollic update: set stack pointer */
+  ldr   sp, =_estack    /* Set stack pointer */
+
+/* Call the clock system initialization function.*/
+    bl  SystemInit
 
 /* Copy the data segment initializers from flash to SRAM */
   movs  r1, #0
@@ -108,8 +93,6 @@ LoopFillZerobss:
     cmp r2, r3
     bcc FillZerobss
 
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
 /* Call static constructors */
     bl __libc_init_array
 /* Call the application's entry point.*/

CMSIS/STM32L4xx/Source/Templates/gcc/startup_stm32l485xx.s

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file      startup_stm32l485xx.s
   * @author    MCD Application Team
-  * @version   V1.3.2
-  * @date      16-June-2017
   * @brief     STM32L485xx devices vector table for GCC toolchain.
   *            This module performs:
   *                - Set the initial SP
@@ -17,29 +15,13 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under Apache License, Version 2.0,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/Apache-2.0
   *
   ******************************************************************************
   */
@@ -78,7 +60,10 @@ defined in linker script */
     .weak   Reset_Handler
     .type   Reset_Handler, %function
 Reset_Handler:
-  ldr   sp, =_estack    /* Atollic update: set stack pointer */
+  ldr   sp, =_estack    /* Set stack pointer */
+
+/* Call the clock system initialization function.*/
+    bl  SystemInit
 
 /* Copy the data segment initializers from flash to SRAM */
   movs  r1, #0
@@ -108,8 +93,6 @@ LoopFillZerobss:
     cmp r2, r3
     bcc FillZerobss
 
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
 /* Call static constructors */
     bl __libc_init_array
 /* Call the application's entry point.*/

CMSIS/STM32L4xx/Source/Templates/gcc/startup_stm32l486xx.s

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file      startup_stm32l486xx.s
   * @author    MCD Application Team
-  * @version   V1.3.2
-  * @date      16-June-2017
   * @brief     STM32L486xx devices vector table for GCC toolchain.
   *            This module performs:
   *                - Set the initial SP
@@ -17,29 +15,13 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under Apache License, Version 2.0,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/Apache-2.0
   *
   ******************************************************************************
   */
@@ -78,7 +60,10 @@ defined in linker script */
     .weak   Reset_Handler
     .type   Reset_Handler, %function
 Reset_Handler:
-  ldr   sp, =_estack    /* Atollic update: set stack pointer */
+  ldr   sp, =_estack    /* Set stack pointer */
+
+/* Call the clock system initialization function.*/
+    bl  SystemInit
 
 /* Copy the data segment initializers from flash to SRAM */
   movs  r1, #0
@@ -108,8 +93,6 @@ LoopFillZerobss:
     cmp r2, r3
     bcc FillZerobss
 
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
 /* Call static constructors */
     bl __libc_init_array
 /* Call the application's entry point.*/

CMSIS/STM32L4xx/Source/Templates/gcc/startup_stm32l496xx.s

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file      startup_stm32l496xx.s
   * @author    MCD Application Team
-  * @version   V1.3.2
-  * @date      16-June-2017
   * @brief     STM32L496xx devices vector table GCC toolchain.
   *            This module performs:
   *                - Set the initial SP
@@ -17,29 +15,13 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under Apache License, Version 2.0,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/Apache-2.0
   *
   ******************************************************************************
   */
@@ -78,7 +60,10 @@ defined in linker script */
     .weak   Reset_Handler
     .type   Reset_Handler, %function
 Reset_Handler:
-  ldr   sp, =_estack    /* Atollic update: set stack pointer */
+  ldr   sp, =_estack    /* Set stack pointer */
+
+/* Call the clock system initialization function.*/
+    bl  SystemInit
 
 /* Copy the data segment initializers from flash to SRAM */
   movs  r1, #0
@@ -108,8 +93,6 @@ LoopFillZerobss:
     cmp r2, r3
     bcc FillZerobss
 
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
 /* Call static constructors */
     bl __libc_init_array
 /* Call the application's entry point.*/

CMSIS/STM32L4xx/Source/Templates/gcc/startup_stm32l4a6xx.s

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file      startup_stm32l4a6xx.s
   * @author    MCD Application Team
-  * @version   V1.3.2
-  * @date      16-June-2017
   * @brief     STM32L4A6xx devices vector table GCC toolchain.
   *            This module performs:
   *                - Set the initial SP
@@ -17,29 +15,13 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under Apache License, Version 2.0,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/Apache-2.0
   *
   ******************************************************************************
   */
@@ -78,7 +60,10 @@ defined in linker script */
     .weak   Reset_Handler
     .type   Reset_Handler, %function
 Reset_Handler:
-  ldr   sp, =_estack    /* Atollic update: set stack pointer */
+  ldr   sp, =_estack    /* Set stack pointer */
+
+/* Call the clock system initialization function.*/
+    bl  SystemInit
 
 /* Copy the data segment initializers from flash to SRAM */
   movs  r1, #0
@@ -108,8 +93,6 @@ LoopFillZerobss:
     cmp r2, r3
     bcc FillZerobss
 
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
 /* Call static constructors */
     bl __libc_init_array
 /* Call the application's entry point.*/

CMSIS/STM32L4xx/Source/Templates/gcc/startup_stm32l4p5xx.s

@@ -0,0 +1,537 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32l4p5xx.s
+  * @author    MCD Application Team
+  * @brief     STM32L4P5xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address,
+  *                - Configure the clock system
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Apache License, Version 2.0,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/Apache-2.0
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+    .cpu cortex-m4
+    .fpu softvfp
+    .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word   _sidata
+/* start address for the .data section. defined in linker script */
+.word   _sdata
+/* end address for the .data section. defined in linker script */
+.word   _edata
+/* start address for the .bss section. defined in linker script */
+.word   _sbss
+/* end address for the .bss section. defined in linker script */
+.word   _ebss
+
+.equ  BootRAM,        0xF1E0F85F
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+    .section    .text.Reset_Handler
+    .weak   Reset_Handler
+    .type   Reset_Handler, %function
+Reset_Handler:
+  ldr   sp, =_estack    /* Set stack pointer */
+
+/* Call the clock system initialization function.*/
+    bl  SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b LoopCopyDataInit
+
+CopyDataInit:
+    ldr r3, =_sidata
+    ldr r3, [r3, r1]
+    str r3, [r0, r1]
+    adds    r1, r1, #4
+
+LoopCopyDataInit:
+    ldr r0, =_sdata
+    ldr r3, =_edata
+    adds    r2, r0, r1
+    cmp r2, r3
+    bcc CopyDataInit
+    ldr r2, =_sbss
+    b   LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+    movs    r3, #0
+    str r3, [r2], #4
+
+LoopFillZerobss:
+    ldr r3, = _ebss
+    cmp r2, r3
+    bcc FillZerobss
+
+/* Call static constructors */
+    bl __libc_init_array
+/* Call the application's entry point.*/
+    bl  main
+
+LoopForever:
+    b LoopForever
+
+.size   Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section    .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+    b   Infinite_Loop
+    .size   Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+    .section    .isr_vector,"a",%progbits
+    .type   g_pfnVectors, %object
+    .size   g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+    .word   _estack
+    .word   Reset_Handler
+    .word   NMI_Handler
+    .word   HardFault_Handler
+    .word   MemManage_Handler
+    .word   BusFault_Handler
+    .word   UsageFault_Handler
+    .word   0
+    .word   0
+    .word   0
+    .word   0
+    .word   SVC_Handler
+    .word   DebugMon_Handler
+    .word   0
+    .word   PendSV_Handler
+    .word   SysTick_Handler
+    .word   WWDG_IRQHandler
+    .word   PVD_PVM_IRQHandler
+    .word   TAMP_STAMP_IRQHandler
+    .word   RTC_WKUP_IRQHandler
+    .word   FLASH_IRQHandler
+    .word   RCC_IRQHandler
+    .word   EXTI0_IRQHandler
+    .word   EXTI1_IRQHandler
+    .word   EXTI2_IRQHandler
+    .word   EXTI3_IRQHandler
+    .word   EXTI4_IRQHandler
+    .word   DMA1_Channel1_IRQHandler
+    .word   DMA1_Channel2_IRQHandler
+    .word   DMA1_Channel3_IRQHandler
+    .word   DMA1_Channel4_IRQHandler
+    .word   DMA1_Channel5_IRQHandler
+    .word   DMA1_Channel6_IRQHandler
+    .word   DMA1_Channel7_IRQHandler
+    .word   ADC1_2_IRQHandler
+    .word   CAN1_TX_IRQHandler
+    .word   CAN1_RX0_IRQHandler
+    .word   CAN1_RX1_IRQHandler
+    .word   CAN1_SCE_IRQHandler
+    .word   EXTI9_5_IRQHandler
+    .word   TIM1_BRK_TIM15_IRQHandler
+    .word   TIM1_UP_TIM16_IRQHandler
+    .word   TIM1_TRG_COM_TIM17_IRQHandler
+    .word   TIM1_CC_IRQHandler
+    .word   TIM2_IRQHandler
+    .word   TIM3_IRQHandler
+    .word   TIM4_IRQHandler
+    .word   I2C1_EV_IRQHandler
+    .word   I2C1_ER_IRQHandler
+    .word   I2C2_EV_IRQHandler
+    .word   I2C2_ER_IRQHandler
+    .word   SPI1_IRQHandler
+    .word   SPI2_IRQHandler
+    .word   USART1_IRQHandler
+    .word   USART2_IRQHandler
+    .word   USART3_IRQHandler
+    .word   EXTI15_10_IRQHandler
+    .word   RTC_Alarm_IRQHandler
+    .word   0
+    .word   TIM8_BRK_IRQHandler
+    .word   TIM8_UP_IRQHandler
+    .word   TIM8_TRG_COM_IRQHandler
+    .word   TIM8_CC_IRQHandler
+    .word   SDMMC2_IRQHandler
+    .word   FMC_IRQHandler
+    .word   SDMMC1_IRQHandler
+    .word   TIM5_IRQHandler
+    .word   SPI3_IRQHandler
+    .word   UART4_IRQHandler
+    .word   UART5_IRQHandler
+    .word   TIM6_DAC_IRQHandler
+    .word   TIM7_IRQHandler
+    .word   DMA2_Channel1_IRQHandler
+    .word   DMA2_Channel2_IRQHandler
+    .word   DMA2_Channel3_IRQHandler
+    .word   DMA2_Channel4_IRQHandler
+    .word   DMA2_Channel5_IRQHandler
+    .word   DFSDM1_FLT0_IRQHandler
+    .word   DFSDM1_FLT1_IRQHandler
+    .word   0
+    .word   COMP_IRQHandler
+    .word   LPTIM1_IRQHandler
+    .word   LPTIM2_IRQHandler
+    .word   OTG_FS_IRQHandler
+    .word   DMA2_Channel6_IRQHandler
+    .word   DMA2_Channel7_IRQHandler
+    .word   LPUART1_IRQHandler
+    .word   OCTOSPI1_IRQHandler
+    .word   I2C3_EV_IRQHandler
+    .word   I2C3_ER_IRQHandler
+    .word   SAI1_IRQHandler
+    .word   SAI2_IRQHandler
+    .word   OCTOSPI2_IRQHandler
+    .word   TSC_IRQHandler
+    .word   0
+    .word   0
+    .word   RNG_IRQHandler
+    .word   FPU_IRQHandler
+    .word   HASH_CRS_IRQHandler
+    .word   I2C4_ER_IRQHandler
+    .word   I2C4_EV_IRQHandler
+    .word   DCMI_PSSI_IRQHandler
+    .word   0
+    .word   0
+    .word   0
+    .word   0
+    .word   DMA2D_IRQHandler
+    .word   LTDC_IRQHandler
+    .word   LTDC_ER_IRQHandler
+    .word   0
+    .word   DMAMUX1_OVR_IRQHandler
+
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+  .weak NMI_Handler
+    .thumb_set NMI_Handler,Default_Handler
+
+  .weak HardFault_Handler
+    .thumb_set HardFault_Handler,Default_Handler
+
+  .weak MemManage_Handler
+    .thumb_set MemManage_Handler,Default_Handler
+
+  .weak BusFault_Handler
+    .thumb_set BusFault_Handler,Default_Handler
+
+    .weak   UsageFault_Handler
+    .thumb_set UsageFault_Handler,Default_Handler
+
+    .weak   SVC_Handler
+    .thumb_set SVC_Handler,Default_Handler
+
+    .weak   DebugMon_Handler
+    .thumb_set DebugMon_Handler,Default_Handler
+
+    .weak   PendSV_Handler
+    .thumb_set PendSV_Handler,Default_Handler
+
+    .weak   SysTick_Handler
+    .thumb_set SysTick_Handler,Default_Handler
+
+    .weak   WWDG_IRQHandler
+    .thumb_set WWDG_IRQHandler,Default_Handler
+
+    .weak   PVD_PVM_IRQHandler
+    .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+    .weak   TAMP_STAMP_IRQHandler
+    .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+    .weak   RTC_WKUP_IRQHandler
+    .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+    .weak   FLASH_IRQHandler
+    .thumb_set FLASH_IRQHandler,Default_Handler
+
+    .weak   RCC_IRQHandler
+    .thumb_set RCC_IRQHandler,Default_Handler
+
+    .weak   EXTI0_IRQHandler
+    .thumb_set EXTI0_IRQHandler,Default_Handler
+
+    .weak   EXTI1_IRQHandler
+    .thumb_set EXTI1_IRQHandler,Default_Handler
+
+    .weak   EXTI2_IRQHandler
+    .thumb_set EXTI2_IRQHandler,Default_Handler
+
+    .weak   EXTI3_IRQHandler
+    .thumb_set EXTI3_IRQHandler,Default_Handler
+
+    .weak   EXTI4_IRQHandler
+    .thumb_set EXTI4_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel1_IRQHandler
+    .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel2_IRQHandler
+    .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel3_IRQHandler
+    .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel4_IRQHandler
+    .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel5_IRQHandler
+    .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel6_IRQHandler
+    .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel7_IRQHandler
+    .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+    .weak   ADC1_2_IRQHandler
+    .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+    .weak   CAN1_TX_IRQHandler
+    .thumb_set CAN1_TX_IRQHandler,Default_Handler
+
+    .weak   CAN1_RX0_IRQHandler
+    .thumb_set CAN1_RX0_IRQHandler,Default_Handler
+
+    .weak   CAN1_RX1_IRQHandler
+    .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+    .weak   CAN1_SCE_IRQHandler
+    .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+    .weak   EXTI9_5_IRQHandler
+    .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+    .weak   TIM1_BRK_TIM15_IRQHandler
+    .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+    .weak   TIM1_UP_TIM16_IRQHandler
+    .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+    .weak   TIM1_TRG_COM_TIM17_IRQHandler
+    .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+    .weak   TIM1_CC_IRQHandler
+    .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+    .weak   TIM2_IRQHandler
+    .thumb_set TIM2_IRQHandler,Default_Handler
+
+    .weak   TIM3_IRQHandler
+    .thumb_set TIM3_IRQHandler,Default_Handler
+
+    .weak   TIM4_IRQHandler
+    .thumb_set TIM4_IRQHandler,Default_Handler
+
+    .weak   I2C1_EV_IRQHandler
+    .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+    .weak   I2C1_ER_IRQHandler
+    .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+    .weak   I2C2_EV_IRQHandler
+    .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+    .weak   I2C2_ER_IRQHandler
+    .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+    .weak   SPI1_IRQHandler
+    .thumb_set SPI1_IRQHandler,Default_Handler
+
+    .weak   SPI2_IRQHandler
+    .thumb_set SPI2_IRQHandler,Default_Handler
+
+    .weak   USART1_IRQHandler
+    .thumb_set USART1_IRQHandler,Default_Handler
+
+    .weak   USART2_IRQHandler
+    .thumb_set USART2_IRQHandler,Default_Handler
+
+    .weak   USART3_IRQHandler
+    .thumb_set USART3_IRQHandler,Default_Handler
+
+    .weak   EXTI15_10_IRQHandler
+    .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+    .weak   RTC_Alarm_IRQHandler
+    .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+    .weak   TIM8_BRK_IRQHandler
+    .thumb_set TIM8_BRK_IRQHandler,Default_Handler
+
+    .weak   TIM8_UP_IRQHandler
+    .thumb_set TIM8_UP_IRQHandler,Default_Handler
+
+    .weak   TIM8_TRG_COM_IRQHandler
+    .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+
+    .weak   TIM8_CC_IRQHandler
+    .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+    .weak   SDMMC2_IRQHandler
+    .thumb_set SDMMC2_IRQHandler,Default_Handler
+
+    .weak   FMC_IRQHandler
+    .thumb_set FMC_IRQHandler,Default_Handler
+
+    .weak   SDMMC1_IRQHandler
+    .thumb_set SDMMC1_IRQHandler,Default_Handler
+
+    .weak   TIM5_IRQHandler
+    .thumb_set TIM5_IRQHandler,Default_Handler
+
+    .weak   SPI3_IRQHandler
+    .thumb_set SPI3_IRQHandler,Default_Handler
+
+    .weak   UART4_IRQHandler
+    .thumb_set UART4_IRQHandler,Default_Handler
+
+    .weak   UART5_IRQHandler
+    .thumb_set UART5_IRQHandler,Default_Handler
+
+    .weak   TIM6_DAC_IRQHandler
+    .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+    .weak   TIM7_IRQHandler
+    .thumb_set TIM7_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel1_IRQHandler
+    .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel2_IRQHandler
+    .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel3_IRQHandler
+    .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel4_IRQHandler
+    .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel5_IRQHandler
+    .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+    .weak   DFSDM1_FLT0_IRQHandler
+    .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+
+    .weak   DFSDM1_FLT1_IRQHandler
+    .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+
+    .weak   COMP_IRQHandler
+    .thumb_set COMP_IRQHandler,Default_Handler
+
+    .weak   LPTIM1_IRQHandler
+    .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+    .weak   LPTIM2_IRQHandler
+    .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+    .weak   OTG_FS_IRQHandler
+    .thumb_set OTG_FS_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel6_IRQHandler
+    .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel7_IRQHandler
+    .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+    .weak   LPUART1_IRQHandler
+    .thumb_set LPUART1_IRQHandler,Default_Handler
+
+    .weak   OCTOSPI1_IRQHandler
+    .thumb_set OCTOSPI1_IRQHandler,Default_Handler
+
+    .weak   I2C3_EV_IRQHandler
+    .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+    .weak   I2C3_ER_IRQHandler
+    .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+    .weak   SAI1_IRQHandler
+    .thumb_set SAI1_IRQHandler,Default_Handler
+
+    .weak   SAI2_IRQHandler
+    .thumb_set SAI2_IRQHandler,Default_Handler
+
+    .weak   OCTOSPI2_IRQHandler
+    .thumb_set OCTOSPI2_IRQHandler,Default_Handler
+
+    .weak   TSC_IRQHandler
+    .thumb_set TSC_IRQHandler,Default_Handler
+
+    .weak   RNG_IRQHandler
+    .thumb_set RNG_IRQHandler,Default_Handler
+
+    .weak   FPU_IRQHandler
+    .thumb_set FPU_IRQHandler,Default_Handler
+
+    .weak   HASH_CRS_IRQHandler
+    .thumb_set HASH_CRS_IRQHandler,Default_Handler
+
+    .weak   I2C4_ER_IRQHandler
+    .thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+    .weak   I2C4_EV_IRQHandler
+    .thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+    .weak   DCMI_PSSI_IRQHandler
+    .thumb_set DCMI_PSSI_IRQHandler,Default_Handler
+
+    .weak   DMA2D_IRQHandler
+    .thumb_set DMA2D_IRQHandler,Default_Handler
+
+    .weak   LTDC_IRQHandler
+    .thumb_set LTDC_IRQHandler,Default_Handler
+
+    .weak   LTDC_ER_IRQHandler
+    .thumb_set LTDC_ER_IRQHandler,Default_Handler
+
+    .weak   DMAMUX1_OVR_IRQHandler
+    .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

CMSIS/STM32L4xx/Source/Templates/gcc/startup_stm32l4q5xx.s

@@ -0,0 +1,543 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32l4q5xx.s
+  * @author    MCD Application Team
+  * @brief     STM32L4Q5xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address,
+  *                - Configure the clock system
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Apache License, Version 2.0,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/Apache-2.0
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+    .cpu cortex-m4
+    .fpu softvfp
+    .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word   _sidata
+/* start address for the .data section. defined in linker script */
+.word   _sdata
+/* end address for the .data section. defined in linker script */
+.word   _edata
+/* start address for the .bss section. defined in linker script */
+.word   _sbss
+/* end address for the .bss section. defined in linker script */
+.word   _ebss
+
+.equ  BootRAM,        0xF1E0F85F
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+    .section    .text.Reset_Handler
+    .weak   Reset_Handler
+    .type   Reset_Handler, %function
+Reset_Handler:
+  ldr   sp, =_estack    /* Set stack pointer */
+
+/* Call the clock system initialization function.*/
+    bl  SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b LoopCopyDataInit
+
+CopyDataInit:
+    ldr r3, =_sidata
+    ldr r3, [r3, r1]
+    str r3, [r0, r1]
+    adds    r1, r1, #4
+
+LoopCopyDataInit:
+    ldr r0, =_sdata
+    ldr r3, =_edata
+    adds    r2, r0, r1
+    cmp r2, r3
+    bcc CopyDataInit
+    ldr r2, =_sbss
+    b   LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+    movs    r3, #0
+    str r3, [r2], #4
+
+LoopFillZerobss:
+    ldr r3, = _ebss
+    cmp r2, r3
+    bcc FillZerobss
+
+/* Call static constructors */
+    bl __libc_init_array
+/* Call the application's entry point.*/
+    bl  main
+
+LoopForever:
+    b LoopForever
+
+.size   Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section    .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+    b   Infinite_Loop
+    .size   Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+    .section    .isr_vector,"a",%progbits
+    .type   g_pfnVectors, %object
+    .size   g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+    .word   _estack
+    .word   Reset_Handler
+    .word   NMI_Handler
+    .word   HardFault_Handler
+    .word   MemManage_Handler
+    .word   BusFault_Handler
+    .word   UsageFault_Handler
+    .word   0
+    .word   0
+    .word   0
+    .word   0
+    .word   SVC_Handler
+    .word   DebugMon_Handler
+    .word   0
+    .word   PendSV_Handler
+    .word   SysTick_Handler
+    .word   WWDG_IRQHandler
+    .word   PVD_PVM_IRQHandler
+    .word   TAMP_STAMP_IRQHandler
+    .word   RTC_WKUP_IRQHandler
+    .word   FLASH_IRQHandler
+    .word   RCC_IRQHandler
+    .word   EXTI0_IRQHandler
+    .word   EXTI1_IRQHandler
+    .word   EXTI2_IRQHandler
+    .word   EXTI3_IRQHandler
+    .word   EXTI4_IRQHandler
+    .word   DMA1_Channel1_IRQHandler
+    .word   DMA1_Channel2_IRQHandler
+    .word   DMA1_Channel3_IRQHandler
+    .word   DMA1_Channel4_IRQHandler
+    .word   DMA1_Channel5_IRQHandler
+    .word   DMA1_Channel6_IRQHandler
+    .word   DMA1_Channel7_IRQHandler
+    .word   ADC1_2_IRQHandler
+    .word   CAN1_TX_IRQHandler
+    .word   CAN1_RX0_IRQHandler
+    .word   CAN1_RX1_IRQHandler
+    .word   CAN1_SCE_IRQHandler
+    .word   EXTI9_5_IRQHandler
+    .word   TIM1_BRK_TIM15_IRQHandler
+    .word   TIM1_UP_TIM16_IRQHandler
+    .word   TIM1_TRG_COM_TIM17_IRQHandler
+    .word   TIM1_CC_IRQHandler
+    .word   TIM2_IRQHandler
+    .word   TIM3_IRQHandler
+    .word   TIM4_IRQHandler
+    .word   I2C1_EV_IRQHandler
+    .word   I2C1_ER_IRQHandler
+    .word   I2C2_EV_IRQHandler
+    .word   I2C2_ER_IRQHandler
+    .word   SPI1_IRQHandler
+    .word   SPI2_IRQHandler
+    .word   USART1_IRQHandler
+    .word   USART2_IRQHandler
+    .word   USART3_IRQHandler
+    .word   EXTI15_10_IRQHandler
+    .word   RTC_Alarm_IRQHandler
+    .word   0
+    .word   TIM8_BRK_IRQHandler
+    .word   TIM8_UP_IRQHandler
+    .word   TIM8_TRG_COM_IRQHandler
+    .word   TIM8_CC_IRQHandler
+    .word   SDMMC2_IRQHandler
+    .word   FMC_IRQHandler
+    .word   SDMMC1_IRQHandler
+    .word   TIM5_IRQHandler
+    .word   SPI3_IRQHandler
+    .word   UART4_IRQHandler
+    .word   UART5_IRQHandler
+    .word   TIM6_DAC_IRQHandler
+    .word   TIM7_IRQHandler
+    .word   DMA2_Channel1_IRQHandler
+    .word   DMA2_Channel2_IRQHandler
+    .word   DMA2_Channel3_IRQHandler
+    .word   DMA2_Channel4_IRQHandler
+    .word   DMA2_Channel5_IRQHandler
+    .word   DFSDM1_FLT0_IRQHandler
+    .word   DFSDM1_FLT1_IRQHandler
+    .word   0
+    .word   COMP_IRQHandler
+    .word   LPTIM1_IRQHandler
+    .word   LPTIM2_IRQHandler
+    .word   OTG_FS_IRQHandler
+    .word   DMA2_Channel6_IRQHandler
+    .word   DMA2_Channel7_IRQHandler
+    .word   LPUART1_IRQHandler
+    .word   OCTOSPI1_IRQHandler
+    .word   I2C3_EV_IRQHandler
+    .word   I2C3_ER_IRQHandler
+    .word   SAI1_IRQHandler
+    .word   SAI2_IRQHandler
+    .word   OCTOSPI2_IRQHandler
+    .word   TSC_IRQHandler
+    .word   0
+    .word   AES_IRQHandler
+    .word   RNG_IRQHandler
+    .word   FPU_IRQHandler
+    .word   HASH_CRS_IRQHandler
+    .word   I2C4_ER_IRQHandler
+    .word   I2C4_EV_IRQHandler
+    .word   DCMI_PSSI_IRQHandler
+    .word   PKA_IRQHandler
+    .word   0
+    .word   0
+    .word   0
+    .word   DMA2D_IRQHandler
+    .word   LTDC_IRQHandler
+    .word   LTDC_ER_IRQHandler
+    .word   0
+    .word   DMAMUX1_OVR_IRQHandler
+
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+  .weak NMI_Handler
+    .thumb_set NMI_Handler,Default_Handler
+
+  .weak HardFault_Handler
+    .thumb_set HardFault_Handler,Default_Handler
+
+  .weak MemManage_Handler
+    .thumb_set MemManage_Handler,Default_Handler
+
+  .weak BusFault_Handler
+    .thumb_set BusFault_Handler,Default_Handler
+
+    .weak   UsageFault_Handler
+    .thumb_set UsageFault_Handler,Default_Handler
+
+    .weak   SVC_Handler
+    .thumb_set SVC_Handler,Default_Handler
+
+    .weak   DebugMon_Handler
+    .thumb_set DebugMon_Handler,Default_Handler
+
+    .weak   PendSV_Handler
+    .thumb_set PendSV_Handler,Default_Handler
+
+    .weak   SysTick_Handler
+    .thumb_set SysTick_Handler,Default_Handler
+
+    .weak   WWDG_IRQHandler
+    .thumb_set WWDG_IRQHandler,Default_Handler
+
+    .weak   PVD_PVM_IRQHandler
+    .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+    .weak   TAMP_STAMP_IRQHandler
+    .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+    .weak   RTC_WKUP_IRQHandler
+    .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+    .weak   FLASH_IRQHandler
+    .thumb_set FLASH_IRQHandler,Default_Handler
+
+    .weak   RCC_IRQHandler
+    .thumb_set RCC_IRQHandler,Default_Handler
+
+    .weak   EXTI0_IRQHandler
+    .thumb_set EXTI0_IRQHandler,Default_Handler
+
+    .weak   EXTI1_IRQHandler
+    .thumb_set EXTI1_IRQHandler,Default_Handler
+
+    .weak   EXTI2_IRQHandler
+    .thumb_set EXTI2_IRQHandler,Default_Handler
+
+    .weak   EXTI3_IRQHandler
+    .thumb_set EXTI3_IRQHandler,Default_Handler
+
+    .weak   EXTI4_IRQHandler
+    .thumb_set EXTI4_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel1_IRQHandler
+    .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel2_IRQHandler
+    .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel3_IRQHandler
+    .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel4_IRQHandler
+    .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel5_IRQHandler
+    .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel6_IRQHandler
+    .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel7_IRQHandler
+    .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+    .weak   ADC1_2_IRQHandler
+    .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+    .weak   CAN1_TX_IRQHandler
+    .thumb_set CAN1_TX_IRQHandler,Default_Handler
+
+    .weak   CAN1_RX0_IRQHandler
+    .thumb_set CAN1_RX0_IRQHandler,Default_Handler
+
+    .weak   CAN1_RX1_IRQHandler
+    .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+    .weak   CAN1_SCE_IRQHandler
+    .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+    .weak   EXTI9_5_IRQHandler
+    .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+    .weak   TIM1_BRK_TIM15_IRQHandler
+    .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+    .weak   TIM1_UP_TIM16_IRQHandler
+    .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+    .weak   TIM1_TRG_COM_TIM17_IRQHandler
+    .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+    .weak   TIM1_CC_IRQHandler
+    .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+    .weak   TIM2_IRQHandler
+    .thumb_set TIM2_IRQHandler,Default_Handler
+
+    .weak   TIM3_IRQHandler
+    .thumb_set TIM3_IRQHandler,Default_Handler
+
+    .weak   TIM4_IRQHandler
+    .thumb_set TIM4_IRQHandler,Default_Handler
+
+    .weak   I2C1_EV_IRQHandler
+    .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+    .weak   I2C1_ER_IRQHandler
+    .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+    .weak   I2C2_EV_IRQHandler
+    .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+    .weak   I2C2_ER_IRQHandler
+    .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+    .weak   SPI1_IRQHandler
+    .thumb_set SPI1_IRQHandler,Default_Handler
+
+    .weak   SPI2_IRQHandler
+    .thumb_set SPI2_IRQHandler,Default_Handler
+
+    .weak   USART1_IRQHandler
+    .thumb_set USART1_IRQHandler,Default_Handler
+
+    .weak   USART2_IRQHandler
+    .thumb_set USART2_IRQHandler,Default_Handler
+
+    .weak   USART3_IRQHandler
+    .thumb_set USART3_IRQHandler,Default_Handler
+
+    .weak   EXTI15_10_IRQHandler
+    .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+    .weak   RTC_Alarm_IRQHandler
+    .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+    .weak   TIM8_BRK_IRQHandler
+    .thumb_set TIM8_BRK_IRQHandler,Default_Handler
+
+    .weak   TIM8_UP_IRQHandler
+    .thumb_set TIM8_UP_IRQHandler,Default_Handler
+
+    .weak   TIM8_TRG_COM_IRQHandler
+    .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+
+    .weak   TIM8_CC_IRQHandler
+    .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+    .weak   SDMMC2_IRQHandler
+    .thumb_set SDMMC2_IRQHandler,Default_Handler
+
+    .weak   FMC_IRQHandler
+    .thumb_set FMC_IRQHandler,Default_Handler
+
+    .weak   SDMMC1_IRQHandler
+    .thumb_set SDMMC1_IRQHandler,Default_Handler
+
+    .weak   TIM5_IRQHandler
+    .thumb_set TIM5_IRQHandler,Default_Handler
+
+    .weak   SPI3_IRQHandler
+    .thumb_set SPI3_IRQHandler,Default_Handler
+
+    .weak   UART4_IRQHandler
+    .thumb_set UART4_IRQHandler,Default_Handler
+
+    .weak   UART5_IRQHandler
+    .thumb_set UART5_IRQHandler,Default_Handler
+
+    .weak   TIM6_DAC_IRQHandler
+    .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+    .weak   TIM7_IRQHandler
+    .thumb_set TIM7_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel1_IRQHandler
+    .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel2_IRQHandler
+    .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel3_IRQHandler
+    .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel4_IRQHandler
+    .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel5_IRQHandler
+    .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+    .weak   DFSDM1_FLT0_IRQHandler
+    .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+
+    .weak   DFSDM1_FLT1_IRQHandler
+    .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+
+    .weak   COMP_IRQHandler
+    .thumb_set COMP_IRQHandler,Default_Handler
+
+    .weak   LPTIM1_IRQHandler
+    .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+    .weak   LPTIM2_IRQHandler
+    .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+    .weak   OTG_FS_IRQHandler
+    .thumb_set OTG_FS_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel6_IRQHandler
+    .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel7_IRQHandler
+    .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+    .weak   LPUART1_IRQHandler
+    .thumb_set LPUART1_IRQHandler,Default_Handler
+
+    .weak   OCTOSPI1_IRQHandler
+    .thumb_set OCTOSPI1_IRQHandler,Default_Handler
+
+    .weak   I2C3_EV_IRQHandler
+    .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+    .weak   I2C3_ER_IRQHandler
+    .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+    .weak   SAI1_IRQHandler
+    .thumb_set SAI1_IRQHandler,Default_Handler
+
+    .weak   SAI2_IRQHandler
+    .thumb_set SAI2_IRQHandler,Default_Handler
+
+    .weak   OCTOSPI2_IRQHandler
+    .thumb_set OCTOSPI2_IRQHandler,Default_Handler
+
+    .weak   TSC_IRQHandler
+    .thumb_set TSC_IRQHandler,Default_Handler
+
+    .weak   AES_IRQHandler
+    .thumb_set AES_IRQHandler,Default_Handler
+
+    .weak   RNG_IRQHandler
+    .thumb_set RNG_IRQHandler,Default_Handler
+
+    .weak   FPU_IRQHandler
+    .thumb_set FPU_IRQHandler,Default_Handler
+
+    .weak   HASH_CRS_IRQHandler
+    .thumb_set HASH_CRS_IRQHandler,Default_Handler
+
+    .weak   I2C4_ER_IRQHandler
+    .thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+    .weak   I2C4_EV_IRQHandler
+    .thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+    .weak   DCMI_PSSI_IRQHandler
+    .thumb_set DCMI_PSSI_IRQHandler,Default_Handler
+
+    .weak   PKA_IRQHandler
+    .thumb_set PKA_IRQHandler,Default_Handler
+
+    .weak   DMA2D_IRQHandler
+    .thumb_set DMA2D_IRQHandler,Default_Handler
+
+    .weak   LTDC_IRQHandler
+    .thumb_set LTDC_IRQHandler,Default_Handler
+
+    .weak   LTDC_ER_IRQHandler
+    .thumb_set LTDC_ER_IRQHandler,Default_Handler
+
+    .weak   DMAMUX1_OVR_IRQHandler
+    .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

CMSIS/STM32L4xx/Source/Templates/gcc/startup_stm32l4r5xx.s

@@ -0,0 +1,543 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32l4r5xx.s
+  * @author    MCD Application Team
+  * @brief     STM32L4R5xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address,
+  *                - Configure the clock system
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Apache License, Version 2.0,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/Apache-2.0
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+    .cpu cortex-m4
+    .fpu softvfp
+    .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word   _sidata
+/* start address for the .data section. defined in linker script */
+.word   _sdata
+/* end address for the .data section. defined in linker script */
+.word   _edata
+/* start address for the .bss section. defined in linker script */
+.word   _sbss
+/* end address for the .bss section. defined in linker script */
+.word   _ebss
+
+.equ  BootRAM,        0xF1E0F85F
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+    .section    .text.Reset_Handler
+    .weak   Reset_Handler
+    .type   Reset_Handler, %function
+Reset_Handler:
+  ldr   sp, =_estack    /* Set stack pointer */
+
+/* Call the clock system initialization function.*/
+    bl  SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b LoopCopyDataInit
+
+CopyDataInit:
+    ldr r3, =_sidata
+    ldr r3, [r3, r1]
+    str r3, [r0, r1]
+    adds    r1, r1, #4
+
+LoopCopyDataInit:
+    ldr r0, =_sdata
+    ldr r3, =_edata
+    adds    r2, r0, r1
+    cmp r2, r3
+    bcc CopyDataInit
+    ldr r2, =_sbss
+    b   LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+    movs    r3, #0
+    str r3, [r2], #4
+
+LoopFillZerobss:
+    ldr r3, = _ebss
+    cmp r2, r3
+    bcc FillZerobss
+
+/* Call static constructors */
+    bl __libc_init_array
+/* Call the application's entry point.*/
+    bl  main
+
+LoopForever:
+    b LoopForever
+
+.size   Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section    .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+    b   Infinite_Loop
+    .size   Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+    .section    .isr_vector,"a",%progbits
+    .type   g_pfnVectors, %object
+    .size   g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+    .word   _estack
+    .word   Reset_Handler
+    .word   NMI_Handler
+    .word   HardFault_Handler
+    .word   MemManage_Handler
+    .word   BusFault_Handler
+    .word   UsageFault_Handler
+    .word   0
+    .word   0
+    .word   0
+    .word   0
+    .word   SVC_Handler
+    .word   DebugMon_Handler
+    .word   0
+    .word   PendSV_Handler
+    .word   SysTick_Handler
+    .word   WWDG_IRQHandler
+    .word   PVD_PVM_IRQHandler
+    .word   TAMP_STAMP_IRQHandler
+    .word   RTC_WKUP_IRQHandler
+    .word   FLASH_IRQHandler
+    .word   RCC_IRQHandler
+    .word   EXTI0_IRQHandler
+    .word   EXTI1_IRQHandler
+    .word   EXTI2_IRQHandler
+    .word   EXTI3_IRQHandler
+    .word   EXTI4_IRQHandler
+    .word   DMA1_Channel1_IRQHandler
+    .word   DMA1_Channel2_IRQHandler
+    .word   DMA1_Channel3_IRQHandler
+    .word   DMA1_Channel4_IRQHandler
+    .word   DMA1_Channel5_IRQHandler
+    .word   DMA1_Channel6_IRQHandler
+    .word   DMA1_Channel7_IRQHandler
+    .word   ADC1_IRQHandler
+    .word   CAN1_TX_IRQHandler
+    .word   CAN1_RX0_IRQHandler
+    .word   CAN1_RX1_IRQHandler
+    .word   CAN1_SCE_IRQHandler
+    .word   EXTI9_5_IRQHandler
+    .word   TIM1_BRK_TIM15_IRQHandler
+    .word   TIM1_UP_TIM16_IRQHandler
+    .word   TIM1_TRG_COM_TIM17_IRQHandler
+    .word   TIM1_CC_IRQHandler
+    .word   TIM2_IRQHandler
+    .word   TIM3_IRQHandler
+    .word   TIM4_IRQHandler
+    .word   I2C1_EV_IRQHandler
+    .word   I2C1_ER_IRQHandler
+    .word   I2C2_EV_IRQHandler
+    .word   I2C2_ER_IRQHandler
+    .word   SPI1_IRQHandler
+    .word   SPI2_IRQHandler
+    .word   USART1_IRQHandler
+    .word   USART2_IRQHandler
+    .word   USART3_IRQHandler
+    .word   EXTI15_10_IRQHandler
+    .word   RTC_Alarm_IRQHandler
+    .word   DFSDM1_FLT3_IRQHandler
+    .word   TIM8_BRK_IRQHandler
+    .word   TIM8_UP_IRQHandler
+    .word   TIM8_TRG_COM_IRQHandler
+    .word   TIM8_CC_IRQHandler
+    .word   0
+    .word   FMC_IRQHandler
+    .word   SDMMC1_IRQHandler
+    .word   TIM5_IRQHandler
+    .word   SPI3_IRQHandler
+    .word   UART4_IRQHandler
+    .word   UART5_IRQHandler
+    .word   TIM6_DAC_IRQHandler
+    .word   TIM7_IRQHandler
+    .word   DMA2_Channel1_IRQHandler
+    .word   DMA2_Channel2_IRQHandler
+    .word   DMA2_Channel3_IRQHandler
+    .word   DMA2_Channel4_IRQHandler
+    .word   DMA2_Channel5_IRQHandler
+    .word   DFSDM1_FLT0_IRQHandler
+    .word   DFSDM1_FLT1_IRQHandler
+    .word   DFSDM1_FLT2_IRQHandler
+    .word   COMP_IRQHandler
+    .word   LPTIM1_IRQHandler
+    .word   LPTIM2_IRQHandler
+    .word   OTG_FS_IRQHandler
+    .word   DMA2_Channel6_IRQHandler
+    .word   DMA2_Channel7_IRQHandler
+    .word   LPUART1_IRQHandler
+    .word   OCTOSPI1_IRQHandler
+    .word   I2C3_EV_IRQHandler
+    .word   I2C3_ER_IRQHandler
+    .word   SAI1_IRQHandler
+    .word   SAI2_IRQHandler
+    .word   OCTOSPI2_IRQHandler
+    .word   TSC_IRQHandler
+    .word   0
+    .word   0
+    .word   RNG_IRQHandler
+    .word   FPU_IRQHandler
+    .word   CRS_IRQHandler
+    .word   I2C4_ER_IRQHandler
+    .word   I2C4_EV_IRQHandler
+    .word   DCMI_IRQHandler
+    .word   0
+    .word   0
+    .word   0
+    .word   0
+    .word   DMA2D_IRQHandler
+    .word   LTDC_IRQHandler
+    .word   LTDC_ER_IRQHandler
+    .word   GFXMMU_IRQHandler
+    .word   DMAMUX1_OVR_IRQHandler
+
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+  .weak NMI_Handler
+    .thumb_set NMI_Handler,Default_Handler
+
+  .weak HardFault_Handler
+    .thumb_set HardFault_Handler,Default_Handler
+
+  .weak MemManage_Handler
+    .thumb_set MemManage_Handler,Default_Handler
+
+  .weak BusFault_Handler
+    .thumb_set BusFault_Handler,Default_Handler
+
+    .weak   UsageFault_Handler
+    .thumb_set UsageFault_Handler,Default_Handler
+
+    .weak   SVC_Handler
+    .thumb_set SVC_Handler,Default_Handler
+
+    .weak   DebugMon_Handler
+    .thumb_set DebugMon_Handler,Default_Handler
+
+    .weak   PendSV_Handler
+    .thumb_set PendSV_Handler,Default_Handler
+
+    .weak   SysTick_Handler
+    .thumb_set SysTick_Handler,Default_Handler
+
+    .weak   WWDG_IRQHandler
+    .thumb_set WWDG_IRQHandler,Default_Handler
+
+    .weak   PVD_PVM_IRQHandler
+    .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+    .weak   TAMP_STAMP_IRQHandler
+    .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+    .weak   RTC_WKUP_IRQHandler
+    .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+    .weak   FLASH_IRQHandler
+    .thumb_set FLASH_IRQHandler,Default_Handler
+
+    .weak   RCC_IRQHandler
+    .thumb_set RCC_IRQHandler,Default_Handler
+
+    .weak   EXTI0_IRQHandler
+    .thumb_set EXTI0_IRQHandler,Default_Handler
+
+    .weak   EXTI1_IRQHandler
+    .thumb_set EXTI1_IRQHandler,Default_Handler
+
+    .weak   EXTI2_IRQHandler
+    .thumb_set EXTI2_IRQHandler,Default_Handler
+
+    .weak   EXTI3_IRQHandler
+    .thumb_set EXTI3_IRQHandler,Default_Handler
+
+    .weak   EXTI4_IRQHandler
+    .thumb_set EXTI4_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel1_IRQHandler
+    .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel2_IRQHandler
+    .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel3_IRQHandler
+    .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel4_IRQHandler
+    .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel5_IRQHandler
+    .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel6_IRQHandler
+    .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel7_IRQHandler
+    .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+    .weak   ADC1_IRQHandler
+    .thumb_set ADC1_IRQHandler,Default_Handler
+
+    .weak   CAN1_TX_IRQHandler
+    .thumb_set CAN1_TX_IRQHandler,Default_Handler
+
+    .weak   CAN1_RX0_IRQHandler
+    .thumb_set CAN1_RX0_IRQHandler,Default_Handler
+
+    .weak   CAN1_RX1_IRQHandler
+    .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+    .weak   CAN1_SCE_IRQHandler
+    .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+    .weak   EXTI9_5_IRQHandler
+    .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+    .weak   TIM1_BRK_TIM15_IRQHandler
+    .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+    .weak   TIM1_UP_TIM16_IRQHandler
+    .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+    .weak   TIM1_TRG_COM_TIM17_IRQHandler
+    .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+    .weak   TIM1_CC_IRQHandler
+    .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+    .weak   TIM2_IRQHandler
+    .thumb_set TIM2_IRQHandler,Default_Handler
+
+    .weak   TIM3_IRQHandler
+    .thumb_set TIM3_IRQHandler,Default_Handler
+
+    .weak   TIM4_IRQHandler
+    .thumb_set TIM4_IRQHandler,Default_Handler
+
+    .weak   I2C1_EV_IRQHandler
+    .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+    .weak   I2C1_ER_IRQHandler
+    .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+    .weak   I2C2_EV_IRQHandler
+    .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+    .weak   I2C2_ER_IRQHandler
+    .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+    .weak   SPI1_IRQHandler
+    .thumb_set SPI1_IRQHandler,Default_Handler
+
+    .weak   SPI2_IRQHandler
+    .thumb_set SPI2_IRQHandler,Default_Handler
+
+    .weak   USART1_IRQHandler
+    .thumb_set USART1_IRQHandler,Default_Handler
+
+    .weak   USART2_IRQHandler
+    .thumb_set USART2_IRQHandler,Default_Handler
+
+    .weak   USART3_IRQHandler
+    .thumb_set USART3_IRQHandler,Default_Handler
+
+    .weak   EXTI15_10_IRQHandler
+    .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+    .weak   RTC_Alarm_IRQHandler
+    .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+    .weak   DFSDM1_FLT3_IRQHandler
+    .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+
+    .weak   TIM8_BRK_IRQHandler
+    .thumb_set TIM8_BRK_IRQHandler,Default_Handler
+
+    .weak   TIM8_UP_IRQHandler
+    .thumb_set TIM8_UP_IRQHandler,Default_Handler
+
+    .weak   TIM8_TRG_COM_IRQHandler
+    .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+
+    .weak   TIM8_CC_IRQHandler
+    .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+    .weak   FMC_IRQHandler
+    .thumb_set FMC_IRQHandler,Default_Handler
+
+    .weak   SDMMC1_IRQHandler
+    .thumb_set SDMMC1_IRQHandler,Default_Handler
+
+    .weak   TIM5_IRQHandler
+    .thumb_set TIM5_IRQHandler,Default_Handler
+
+    .weak   SPI3_IRQHandler
+    .thumb_set SPI3_IRQHandler,Default_Handler
+
+    .weak   UART4_IRQHandler
+    .thumb_set UART4_IRQHandler,Default_Handler
+
+    .weak   UART5_IRQHandler
+    .thumb_set UART5_IRQHandler,Default_Handler
+
+    .weak   TIM6_DAC_IRQHandler
+    .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+    .weak   TIM7_IRQHandler
+    .thumb_set TIM7_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel1_IRQHandler
+    .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel2_IRQHandler
+    .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel3_IRQHandler
+    .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel4_IRQHandler
+    .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel5_IRQHandler
+    .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+    .weak   DFSDM1_FLT0_IRQHandler
+    .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+
+    .weak   DFSDM1_FLT1_IRQHandler
+    .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+
+    .weak   DFSDM1_FLT2_IRQHandler
+    .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+
+    .weak   COMP_IRQHandler
+    .thumb_set COMP_IRQHandler,Default_Handler
+
+    .weak   LPTIM1_IRQHandler
+    .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+    .weak   LPTIM2_IRQHandler
+    .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+    .weak   OTG_FS_IRQHandler
+    .thumb_set OTG_FS_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel6_IRQHandler
+    .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel7_IRQHandler
+    .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+    .weak   LPUART1_IRQHandler
+    .thumb_set LPUART1_IRQHandler,Default_Handler
+
+    .weak   OCTOSPI1_IRQHandler
+    .thumb_set OCTOSPI1_IRQHandler,Default_Handler
+
+    .weak   I2C3_EV_IRQHandler
+    .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+    .weak   I2C3_ER_IRQHandler
+    .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+    .weak   SAI1_IRQHandler
+    .thumb_set SAI1_IRQHandler,Default_Handler
+
+    .weak   SAI2_IRQHandler
+    .thumb_set SAI2_IRQHandler,Default_Handler
+
+    .weak   OCTOSPI2_IRQHandler
+    .thumb_set OCTOSPI2_IRQHandler,Default_Handler
+
+    .weak   TSC_IRQHandler
+    .thumb_set TSC_IRQHandler,Default_Handler
+
+    .weak   RNG_IRQHandler
+    .thumb_set RNG_IRQHandler,Default_Handler
+
+    .weak   FPU_IRQHandler
+    .thumb_set FPU_IRQHandler,Default_Handler
+
+    .weak   CRS_IRQHandler
+    .thumb_set CRS_IRQHandler,Default_Handler
+
+    .weak   I2C4_ER_IRQHandler
+    .thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+    .weak   I2C4_EV_IRQHandler
+    .thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+    .weak   DCMI_IRQHandler
+    .thumb_set DCMI_IRQHandler,Default_Handler
+
+    .weak   DMA2D_IRQHandler
+    .thumb_set DMA2D_IRQHandler,Default_Handler
+
+    .weak   LTDC_IRQHandler
+    .thumb_set LTDC_IRQHandler,Default_Handler
+
+    .weak   LTDC_ER_IRQHandler
+    .thumb_set LTDC_ER_IRQHandler,Default_Handler
+
+    .weak   GFXMMU_IRQHandler
+    .thumb_set GFXMMU_IRQHandler,Default_Handler
+
+    .weak   DMAMUX1_OVR_IRQHandler
+    .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

CMSIS/STM32L4xx/Source/Templates/gcc/startup_stm32l4r7xx.s

@@ -0,0 +1,543 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32l4r7xx.s
+  * @author    MCD Application Team
+  * @brief     STM32L4R7xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address,
+  *                - Configure the clock system
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Apache License, Version 2.0,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/Apache-2.0
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+    .cpu cortex-m4
+    .fpu softvfp
+    .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word   _sidata
+/* start address for the .data section. defined in linker script */
+.word   _sdata
+/* end address for the .data section. defined in linker script */
+.word   _edata
+/* start address for the .bss section. defined in linker script */
+.word   _sbss
+/* end address for the .bss section. defined in linker script */
+.word   _ebss
+
+.equ  BootRAM,        0xF1E0F85F
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+    .section    .text.Reset_Handler
+    .weak   Reset_Handler
+    .type   Reset_Handler, %function
+Reset_Handler:
+  ldr   sp, =_estack    /* Set stack pointer */
+
+/* Call the clock system initialization function.*/
+    bl  SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b LoopCopyDataInit
+
+CopyDataInit:
+    ldr r3, =_sidata
+    ldr r3, [r3, r1]
+    str r3, [r0, r1]
+    adds    r1, r1, #4
+
+LoopCopyDataInit:
+    ldr r0, =_sdata
+    ldr r3, =_edata
+    adds    r2, r0, r1
+    cmp r2, r3
+    bcc CopyDataInit
+    ldr r2, =_sbss
+    b   LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+    movs    r3, #0
+    str r3, [r2], #4
+
+LoopFillZerobss:
+    ldr r3, = _ebss
+    cmp r2, r3
+    bcc FillZerobss
+
+/* Call static constructors */
+    bl __libc_init_array
+/* Call the application's entry point.*/
+    bl  main
+
+LoopForever:
+    b LoopForever
+
+.size   Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section    .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+    b   Infinite_Loop
+    .size   Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+    .section    .isr_vector,"a",%progbits
+    .type   g_pfnVectors, %object
+    .size   g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+    .word   _estack
+    .word   Reset_Handler
+    .word   NMI_Handler
+    .word   HardFault_Handler
+    .word   MemManage_Handler
+    .word   BusFault_Handler
+    .word   UsageFault_Handler
+    .word   0
+    .word   0
+    .word   0
+    .word   0
+    .word   SVC_Handler
+    .word   DebugMon_Handler
+    .word   0
+    .word   PendSV_Handler
+    .word   SysTick_Handler
+    .word   WWDG_IRQHandler
+    .word   PVD_PVM_IRQHandler
+    .word   TAMP_STAMP_IRQHandler
+    .word   RTC_WKUP_IRQHandler
+    .word   FLASH_IRQHandler
+    .word   RCC_IRQHandler
+    .word   EXTI0_IRQHandler
+    .word   EXTI1_IRQHandler
+    .word   EXTI2_IRQHandler
+    .word   EXTI3_IRQHandler
+    .word   EXTI4_IRQHandler
+    .word   DMA1_Channel1_IRQHandler
+    .word   DMA1_Channel2_IRQHandler
+    .word   DMA1_Channel3_IRQHandler
+    .word   DMA1_Channel4_IRQHandler
+    .word   DMA1_Channel5_IRQHandler
+    .word   DMA1_Channel6_IRQHandler
+    .word   DMA1_Channel7_IRQHandler
+    .word   ADC1_IRQHandler
+    .word   CAN1_TX_IRQHandler
+    .word   CAN1_RX0_IRQHandler
+    .word   CAN1_RX1_IRQHandler
+    .word   CAN1_SCE_IRQHandler
+    .word   EXTI9_5_IRQHandler
+    .word   TIM1_BRK_TIM15_IRQHandler
+    .word   TIM1_UP_TIM16_IRQHandler
+    .word   TIM1_TRG_COM_TIM17_IRQHandler
+    .word   TIM1_CC_IRQHandler
+    .word   TIM2_IRQHandler
+    .word   TIM3_IRQHandler
+    .word   TIM4_IRQHandler
+    .word   I2C1_EV_IRQHandler
+    .word   I2C1_ER_IRQHandler
+    .word   I2C2_EV_IRQHandler
+    .word   I2C2_ER_IRQHandler
+    .word   SPI1_IRQHandler
+    .word   SPI2_IRQHandler
+    .word   USART1_IRQHandler
+    .word   USART2_IRQHandler
+    .word   USART3_IRQHandler
+    .word   EXTI15_10_IRQHandler
+    .word   RTC_Alarm_IRQHandler
+    .word   DFSDM1_FLT3_IRQHandler
+    .word   TIM8_BRK_IRQHandler
+    .word   TIM8_UP_IRQHandler
+    .word   TIM8_TRG_COM_IRQHandler
+    .word   TIM8_CC_IRQHandler
+    .word   0
+    .word   FMC_IRQHandler
+    .word   SDMMC1_IRQHandler
+    .word   TIM5_IRQHandler
+    .word   SPI3_IRQHandler
+    .word   UART4_IRQHandler
+    .word   UART5_IRQHandler
+    .word   TIM6_DAC_IRQHandler
+    .word   TIM7_IRQHandler
+    .word   DMA2_Channel1_IRQHandler
+    .word   DMA2_Channel2_IRQHandler
+    .word   DMA2_Channel3_IRQHandler
+    .word   DMA2_Channel4_IRQHandler
+    .word   DMA2_Channel5_IRQHandler
+    .word   DFSDM1_FLT0_IRQHandler
+    .word   DFSDM1_FLT1_IRQHandler
+    .word   DFSDM1_FLT2_IRQHandler
+    .word   COMP_IRQHandler
+    .word   LPTIM1_IRQHandler
+    .word   LPTIM2_IRQHandler
+    .word   OTG_FS_IRQHandler
+    .word   DMA2_Channel6_IRQHandler
+    .word   DMA2_Channel7_IRQHandler
+    .word   LPUART1_IRQHandler
+    .word   OCTOSPI1_IRQHandler
+    .word   I2C3_EV_IRQHandler
+    .word   I2C3_ER_IRQHandler
+    .word   SAI1_IRQHandler
+    .word   SAI2_IRQHandler
+    .word   OCTOSPI2_IRQHandler
+    .word   TSC_IRQHandler
+    .word   0
+    .word   0
+    .word   RNG_IRQHandler
+    .word   FPU_IRQHandler
+    .word   CRS_IRQHandler
+    .word   I2C4_ER_IRQHandler
+    .word   I2C4_EV_IRQHandler
+    .word   DCMI_IRQHandler
+    .word   0
+    .word   0
+    .word   0
+    .word   0
+    .word   DMA2D_IRQHandler
+    .word   LTDC_IRQHandler
+    .word   LTDC_ER_IRQHandler
+    .word   GFXMMU_IRQHandler
+    .word   DMAMUX1_OVR_IRQHandler
+
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+  .weak NMI_Handler
+    .thumb_set NMI_Handler,Default_Handler
+
+  .weak HardFault_Handler
+    .thumb_set HardFault_Handler,Default_Handler
+
+  .weak MemManage_Handler
+    .thumb_set MemManage_Handler,Default_Handler
+
+  .weak BusFault_Handler
+    .thumb_set BusFault_Handler,Default_Handler
+
+    .weak   UsageFault_Handler
+    .thumb_set UsageFault_Handler,Default_Handler
+
+    .weak   SVC_Handler
+    .thumb_set SVC_Handler,Default_Handler
+
+    .weak   DebugMon_Handler
+    .thumb_set DebugMon_Handler,Default_Handler
+
+    .weak   PendSV_Handler
+    .thumb_set PendSV_Handler,Default_Handler
+
+    .weak   SysTick_Handler
+    .thumb_set SysTick_Handler,Default_Handler
+
+    .weak   WWDG_IRQHandler
+    .thumb_set WWDG_IRQHandler,Default_Handler
+
+    .weak   PVD_PVM_IRQHandler
+    .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+    .weak   TAMP_STAMP_IRQHandler
+    .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+    .weak   RTC_WKUP_IRQHandler
+    .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+    .weak   FLASH_IRQHandler
+    .thumb_set FLASH_IRQHandler,Default_Handler
+
+    .weak   RCC_IRQHandler
+    .thumb_set RCC_IRQHandler,Default_Handler
+
+    .weak   EXTI0_IRQHandler
+    .thumb_set EXTI0_IRQHandler,Default_Handler
+
+    .weak   EXTI1_IRQHandler
+    .thumb_set EXTI1_IRQHandler,Default_Handler
+
+    .weak   EXTI2_IRQHandler
+    .thumb_set EXTI2_IRQHandler,Default_Handler
+
+    .weak   EXTI3_IRQHandler
+    .thumb_set EXTI3_IRQHandler,Default_Handler
+
+    .weak   EXTI4_IRQHandler
+    .thumb_set EXTI4_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel1_IRQHandler
+    .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel2_IRQHandler
+    .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel3_IRQHandler
+    .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel4_IRQHandler
+    .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel5_IRQHandler
+    .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel6_IRQHandler
+    .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel7_IRQHandler
+    .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+    .weak   ADC1_IRQHandler
+    .thumb_set ADC1_IRQHandler,Default_Handler
+
+    .weak   CAN1_TX_IRQHandler
+    .thumb_set CAN1_TX_IRQHandler,Default_Handler
+
+    .weak   CAN1_RX0_IRQHandler
+    .thumb_set CAN1_RX0_IRQHandler,Default_Handler
+
+    .weak   CAN1_RX1_IRQHandler
+    .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+    .weak   CAN1_SCE_IRQHandler
+    .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+    .weak   EXTI9_5_IRQHandler
+    .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+    .weak   TIM1_BRK_TIM15_IRQHandler
+    .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+    .weak   TIM1_UP_TIM16_IRQHandler
+    .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+    .weak   TIM1_TRG_COM_TIM17_IRQHandler
+    .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+    .weak   TIM1_CC_IRQHandler
+    .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+    .weak   TIM2_IRQHandler
+    .thumb_set TIM2_IRQHandler,Default_Handler
+
+    .weak   TIM3_IRQHandler
+    .thumb_set TIM3_IRQHandler,Default_Handler
+
+    .weak   TIM4_IRQHandler
+    .thumb_set TIM4_IRQHandler,Default_Handler
+
+    .weak   I2C1_EV_IRQHandler
+    .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+    .weak   I2C1_ER_IRQHandler
+    .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+    .weak   I2C2_EV_IRQHandler
+    .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+    .weak   I2C2_ER_IRQHandler
+    .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+    .weak   SPI1_IRQHandler
+    .thumb_set SPI1_IRQHandler,Default_Handler
+
+    .weak   SPI2_IRQHandler
+    .thumb_set SPI2_IRQHandler,Default_Handler
+
+    .weak   USART1_IRQHandler
+    .thumb_set USART1_IRQHandler,Default_Handler
+
+    .weak   USART2_IRQHandler
+    .thumb_set USART2_IRQHandler,Default_Handler
+
+    .weak   USART3_IRQHandler
+    .thumb_set USART3_IRQHandler,Default_Handler
+
+    .weak   EXTI15_10_IRQHandler
+    .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+    .weak   RTC_Alarm_IRQHandler
+    .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+    .weak   DFSDM1_FLT3_IRQHandler
+    .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+
+    .weak   TIM8_BRK_IRQHandler
+    .thumb_set TIM8_BRK_IRQHandler,Default_Handler
+
+    .weak   TIM8_UP_IRQHandler
+    .thumb_set TIM8_UP_IRQHandler,Default_Handler
+
+    .weak   TIM8_TRG_COM_IRQHandler
+    .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+
+    .weak   TIM8_CC_IRQHandler
+    .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+    .weak   FMC_IRQHandler
+    .thumb_set FMC_IRQHandler,Default_Handler
+
+    .weak   SDMMC1_IRQHandler
+    .thumb_set SDMMC1_IRQHandler,Default_Handler
+
+    .weak   TIM5_IRQHandler
+    .thumb_set TIM5_IRQHandler,Default_Handler
+
+    .weak   SPI3_IRQHandler
+    .thumb_set SPI3_IRQHandler,Default_Handler
+
+    .weak   UART4_IRQHandler
+    .thumb_set UART4_IRQHandler,Default_Handler
+
+    .weak   UART5_IRQHandler
+    .thumb_set UART5_IRQHandler,Default_Handler
+
+    .weak   TIM6_DAC_IRQHandler
+    .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+    .weak   TIM7_IRQHandler
+    .thumb_set TIM7_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel1_IRQHandler
+    .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel2_IRQHandler
+    .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel3_IRQHandler
+    .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel4_IRQHandler
+    .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel5_IRQHandler
+    .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+    .weak   DFSDM1_FLT0_IRQHandler
+    .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+
+    .weak   DFSDM1_FLT1_IRQHandler
+    .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+
+    .weak   DFSDM1_FLT2_IRQHandler
+    .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+
+    .weak   COMP_IRQHandler
+    .thumb_set COMP_IRQHandler,Default_Handler
+
+    .weak   LPTIM1_IRQHandler
+    .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+    .weak   LPTIM2_IRQHandler
+    .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+    .weak   OTG_FS_IRQHandler
+    .thumb_set OTG_FS_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel6_IRQHandler
+    .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel7_IRQHandler
+    .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+    .weak   LPUART1_IRQHandler
+    .thumb_set LPUART1_IRQHandler,Default_Handler
+
+    .weak   OCTOSPI1_IRQHandler
+    .thumb_set OCTOSPI1_IRQHandler,Default_Handler
+
+    .weak   I2C3_EV_IRQHandler
+    .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+    .weak   I2C3_ER_IRQHandler
+    .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+    .weak   SAI1_IRQHandler
+    .thumb_set SAI1_IRQHandler,Default_Handler
+
+    .weak   SAI2_IRQHandler
+    .thumb_set SAI2_IRQHandler,Default_Handler
+
+    .weak   OCTOSPI2_IRQHandler
+    .thumb_set OCTOSPI2_IRQHandler,Default_Handler
+
+    .weak   TSC_IRQHandler
+    .thumb_set TSC_IRQHandler,Default_Handler
+
+    .weak   RNG_IRQHandler
+    .thumb_set RNG_IRQHandler,Default_Handler
+
+    .weak   FPU_IRQHandler
+    .thumb_set FPU_IRQHandler,Default_Handler
+
+    .weak   CRS_IRQHandler
+    .thumb_set CRS_IRQHandler,Default_Handler
+
+    .weak   I2C4_ER_IRQHandler
+    .thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+    .weak   I2C4_EV_IRQHandler
+    .thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+    .weak   DCMI_IRQHandler
+    .thumb_set DCMI_IRQHandler,Default_Handler
+
+    .weak   DMA2D_IRQHandler
+    .thumb_set DMA2D_IRQHandler,Default_Handler
+
+    .weak   LTDC_IRQHandler
+    .thumb_set LTDC_IRQHandler,Default_Handler
+
+    .weak   LTDC_ER_IRQHandler
+    .thumb_set LTDC_ER_IRQHandler,Default_Handler
+
+    .weak   GFXMMU_IRQHandler
+    .thumb_set GFXMMU_IRQHandler,Default_Handler
+
+    .weak   DMAMUX1_OVR_IRQHandler
+    .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

CMSIS/STM32L4xx/Source/Templates/gcc/startup_stm32l4r9xx.s

@@ -0,0 +1,546 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32l4r9xx.s
+  * @author    MCD Application Team
+  * @brief     STM32L4R9xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address,
+  *                - Configure the clock system
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Apache License, Version 2.0,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/Apache-2.0
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+    .cpu cortex-m4
+    .fpu softvfp
+    .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word   _sidata
+/* start address for the .data section. defined in linker script */
+.word   _sdata
+/* end address for the .data section. defined in linker script */
+.word   _edata
+/* start address for the .bss section. defined in linker script */
+.word   _sbss
+/* end address for the .bss section. defined in linker script */
+.word   _ebss
+
+.equ  BootRAM,        0xF1E0F85F
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+    .section    .text.Reset_Handler
+    .weak   Reset_Handler
+    .type   Reset_Handler, %function
+Reset_Handler:
+  ldr   sp, =_estack    /* Set stack pointer */
+
+/* Call the clock system initialization function.*/
+    bl  SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b LoopCopyDataInit
+
+CopyDataInit:
+    ldr r3, =_sidata
+    ldr r3, [r3, r1]
+    str r3, [r0, r1]
+    adds    r1, r1, #4
+
+LoopCopyDataInit:
+    ldr r0, =_sdata
+    ldr r3, =_edata
+    adds    r2, r0, r1
+    cmp r2, r3
+    bcc CopyDataInit
+    ldr r2, =_sbss
+    b   LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+    movs    r3, #0
+    str r3, [r2], #4
+
+LoopFillZerobss:
+    ldr r3, = _ebss
+    cmp r2, r3
+    bcc FillZerobss
+
+/* Call static constructors */
+    bl __libc_init_array
+/* Call the application's entry point.*/
+    bl  main
+
+LoopForever:
+    b LoopForever
+
+.size   Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section    .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+    b   Infinite_Loop
+    .size   Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+    .section    .isr_vector,"a",%progbits
+    .type   g_pfnVectors, %object
+    .size   g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+    .word   _estack
+    .word   Reset_Handler
+    .word   NMI_Handler
+    .word   HardFault_Handler
+    .word   MemManage_Handler
+    .word   BusFault_Handler
+    .word   UsageFault_Handler
+    .word   0
+    .word   0
+    .word   0
+    .word   0
+    .word   SVC_Handler
+    .word   DebugMon_Handler
+    .word   0
+    .word   PendSV_Handler
+    .word   SysTick_Handler
+    .word   WWDG_IRQHandler
+    .word   PVD_PVM_IRQHandler
+    .word   TAMP_STAMP_IRQHandler
+    .word   RTC_WKUP_IRQHandler
+    .word   FLASH_IRQHandler
+    .word   RCC_IRQHandler
+    .word   EXTI0_IRQHandler
+    .word   EXTI1_IRQHandler
+    .word   EXTI2_IRQHandler
+    .word   EXTI3_IRQHandler
+    .word   EXTI4_IRQHandler
+    .word   DMA1_Channel1_IRQHandler
+    .word   DMA1_Channel2_IRQHandler
+    .word   DMA1_Channel3_IRQHandler
+    .word   DMA1_Channel4_IRQHandler
+    .word   DMA1_Channel5_IRQHandler
+    .word   DMA1_Channel6_IRQHandler
+    .word   DMA1_Channel7_IRQHandler
+    .word   ADC1_IRQHandler
+    .word   CAN1_TX_IRQHandler
+    .word   CAN1_RX0_IRQHandler
+    .word   CAN1_RX1_IRQHandler
+    .word   CAN1_SCE_IRQHandler
+    .word   EXTI9_5_IRQHandler
+    .word   TIM1_BRK_TIM15_IRQHandler
+    .word   TIM1_UP_TIM16_IRQHandler
+    .word   TIM1_TRG_COM_TIM17_IRQHandler
+    .word   TIM1_CC_IRQHandler
+    .word   TIM2_IRQHandler
+    .word   TIM3_IRQHandler
+    .word   TIM4_IRQHandler
+    .word   I2C1_EV_IRQHandler
+    .word   I2C1_ER_IRQHandler
+    .word   I2C2_EV_IRQHandler
+    .word   I2C2_ER_IRQHandler
+    .word   SPI1_IRQHandler
+    .word   SPI2_IRQHandler
+    .word   USART1_IRQHandler
+    .word   USART2_IRQHandler
+    .word   USART3_IRQHandler
+    .word   EXTI15_10_IRQHandler
+    .word   RTC_Alarm_IRQHandler
+    .word   DFSDM1_FLT3_IRQHandler
+    .word   TIM8_BRK_IRQHandler
+    .word   TIM8_UP_IRQHandler
+    .word   TIM8_TRG_COM_IRQHandler
+    .word   TIM8_CC_IRQHandler
+    .word   0
+    .word   FMC_IRQHandler
+    .word   SDMMC1_IRQHandler
+    .word   TIM5_IRQHandler
+    .word   SPI3_IRQHandler
+    .word   UART4_IRQHandler
+    .word   UART5_IRQHandler
+    .word   TIM6_DAC_IRQHandler
+    .word   TIM7_IRQHandler
+    .word   DMA2_Channel1_IRQHandler
+    .word   DMA2_Channel2_IRQHandler
+    .word   DMA2_Channel3_IRQHandler
+    .word   DMA2_Channel4_IRQHandler
+    .word   DMA2_Channel5_IRQHandler
+    .word   DFSDM1_FLT0_IRQHandler
+    .word   DFSDM1_FLT1_IRQHandler
+    .word   DFSDM1_FLT2_IRQHandler
+    .word   COMP_IRQHandler
+    .word   LPTIM1_IRQHandler
+    .word   LPTIM2_IRQHandler
+    .word   OTG_FS_IRQHandler
+    .word   DMA2_Channel6_IRQHandler
+    .word   DMA2_Channel7_IRQHandler
+    .word   LPUART1_IRQHandler
+    .word   OCTOSPI1_IRQHandler
+    .word   I2C3_EV_IRQHandler
+    .word   I2C3_ER_IRQHandler
+    .word   SAI1_IRQHandler
+    .word   SAI2_IRQHandler
+    .word   OCTOSPI2_IRQHandler
+    .word   TSC_IRQHandler
+    .word   DSI_IRQHandler
+    .word   0
+    .word   RNG_IRQHandler
+    .word   FPU_IRQHandler
+    .word   CRS_IRQHandler
+    .word   I2C4_ER_IRQHandler
+    .word   I2C4_EV_IRQHandler
+    .word   DCMI_IRQHandler
+    .word   0
+    .word   0
+    .word   0
+    .word   0
+    .word   DMA2D_IRQHandler
+    .word   LTDC_IRQHandler
+    .word   LTDC_ER_IRQHandler
+    .word   GFXMMU_IRQHandler
+    .word   DMAMUX1_OVR_IRQHandler
+
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+  .weak NMI_Handler
+    .thumb_set NMI_Handler,Default_Handler
+
+  .weak HardFault_Handler
+    .thumb_set HardFault_Handler,Default_Handler
+
+  .weak MemManage_Handler
+    .thumb_set MemManage_Handler,Default_Handler
+
+  .weak BusFault_Handler
+    .thumb_set BusFault_Handler,Default_Handler
+
+    .weak   UsageFault_Handler
+    .thumb_set UsageFault_Handler,Default_Handler
+
+    .weak   SVC_Handler
+    .thumb_set SVC_Handler,Default_Handler
+
+    .weak   DebugMon_Handler
+    .thumb_set DebugMon_Handler,Default_Handler
+
+    .weak   PendSV_Handler
+    .thumb_set PendSV_Handler,Default_Handler
+
+    .weak   SysTick_Handler
+    .thumb_set SysTick_Handler,Default_Handler
+
+    .weak   WWDG_IRQHandler
+    .thumb_set WWDG_IRQHandler,Default_Handler
+
+    .weak   PVD_PVM_IRQHandler
+    .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+    .weak   TAMP_STAMP_IRQHandler
+    .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+    .weak   RTC_WKUP_IRQHandler
+    .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+    .weak   FLASH_IRQHandler
+    .thumb_set FLASH_IRQHandler,Default_Handler
+
+    .weak   RCC_IRQHandler
+    .thumb_set RCC_IRQHandler,Default_Handler
+
+    .weak   EXTI0_IRQHandler
+    .thumb_set EXTI0_IRQHandler,Default_Handler
+
+    .weak   EXTI1_IRQHandler
+    .thumb_set EXTI1_IRQHandler,Default_Handler
+
+    .weak   EXTI2_IRQHandler
+    .thumb_set EXTI2_IRQHandler,Default_Handler
+
+    .weak   EXTI3_IRQHandler
+    .thumb_set EXTI3_IRQHandler,Default_Handler
+
+    .weak   EXTI4_IRQHandler
+    .thumb_set EXTI4_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel1_IRQHandler
+    .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel2_IRQHandler
+    .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel3_IRQHandler
+    .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel4_IRQHandler
+    .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel5_IRQHandler
+    .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel6_IRQHandler
+    .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel7_IRQHandler
+    .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+    .weak   ADC1_IRQHandler
+    .thumb_set ADC1_IRQHandler,Default_Handler
+
+    .weak   CAN1_TX_IRQHandler
+    .thumb_set CAN1_TX_IRQHandler,Default_Handler
+
+    .weak   CAN1_RX0_IRQHandler
+    .thumb_set CAN1_RX0_IRQHandler,Default_Handler
+
+    .weak   CAN1_RX1_IRQHandler
+    .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+    .weak   CAN1_SCE_IRQHandler
+    .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+    .weak   EXTI9_5_IRQHandler
+    .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+    .weak   TIM1_BRK_TIM15_IRQHandler
+    .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+    .weak   TIM1_UP_TIM16_IRQHandler
+    .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+    .weak   TIM1_TRG_COM_TIM17_IRQHandler
+    .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+    .weak   TIM1_CC_IRQHandler
+    .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+    .weak   TIM2_IRQHandler
+    .thumb_set TIM2_IRQHandler,Default_Handler
+
+    .weak   TIM3_IRQHandler
+    .thumb_set TIM3_IRQHandler,Default_Handler
+
+    .weak   TIM4_IRQHandler
+    .thumb_set TIM4_IRQHandler,Default_Handler
+
+    .weak   I2C1_EV_IRQHandler
+    .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+    .weak   I2C1_ER_IRQHandler
+    .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+    .weak   I2C2_EV_IRQHandler
+    .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+    .weak   I2C2_ER_IRQHandler
+    .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+    .weak   SPI1_IRQHandler
+    .thumb_set SPI1_IRQHandler,Default_Handler
+
+    .weak   SPI2_IRQHandler
+    .thumb_set SPI2_IRQHandler,Default_Handler
+
+    .weak   USART1_IRQHandler
+    .thumb_set USART1_IRQHandler,Default_Handler
+
+    .weak   USART2_IRQHandler
+    .thumb_set USART2_IRQHandler,Default_Handler
+
+    .weak   USART3_IRQHandler
+    .thumb_set USART3_IRQHandler,Default_Handler
+
+    .weak   EXTI15_10_IRQHandler
+    .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+    .weak   RTC_Alarm_IRQHandler
+    .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+    .weak   DFSDM1_FLT3_IRQHandler
+    .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+
+    .weak   TIM8_BRK_IRQHandler
+    .thumb_set TIM8_BRK_IRQHandler,Default_Handler
+
+    .weak   TIM8_UP_IRQHandler
+    .thumb_set TIM8_UP_IRQHandler,Default_Handler
+
+    .weak   TIM8_TRG_COM_IRQHandler
+    .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+
+    .weak   TIM8_CC_IRQHandler
+    .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+    .weak   FMC_IRQHandler
+    .thumb_set FMC_IRQHandler,Default_Handler
+
+    .weak   SDMMC1_IRQHandler
+    .thumb_set SDMMC1_IRQHandler,Default_Handler
+
+    .weak   TIM5_IRQHandler
+    .thumb_set TIM5_IRQHandler,Default_Handler
+
+    .weak   SPI3_IRQHandler
+    .thumb_set SPI3_IRQHandler,Default_Handler
+
+    .weak   UART4_IRQHandler
+    .thumb_set UART4_IRQHandler,Default_Handler
+
+    .weak   UART5_IRQHandler
+    .thumb_set UART5_IRQHandler,Default_Handler
+
+    .weak   TIM6_DAC_IRQHandler
+    .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+    .weak   TIM7_IRQHandler
+    .thumb_set TIM7_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel1_IRQHandler
+    .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel2_IRQHandler
+    .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel3_IRQHandler
+    .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel4_IRQHandler
+    .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel5_IRQHandler
+    .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+    .weak   DFSDM1_FLT0_IRQHandler
+    .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+
+    .weak   DFSDM1_FLT1_IRQHandler
+    .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+
+    .weak   DFSDM1_FLT2_IRQHandler
+    .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+
+    .weak   COMP_IRQHandler
+    .thumb_set COMP_IRQHandler,Default_Handler
+
+    .weak   LPTIM1_IRQHandler
+    .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+    .weak   LPTIM2_IRQHandler
+    .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+    .weak   OTG_FS_IRQHandler
+    .thumb_set OTG_FS_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel6_IRQHandler
+    .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel7_IRQHandler
+    .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+    .weak   LPUART1_IRQHandler
+    .thumb_set LPUART1_IRQHandler,Default_Handler
+
+    .weak   OCTOSPI1_IRQHandler
+    .thumb_set OCTOSPI1_IRQHandler,Default_Handler
+
+    .weak   I2C3_EV_IRQHandler
+    .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+    .weak   I2C3_ER_IRQHandler
+    .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+    .weak   SAI1_IRQHandler
+    .thumb_set SAI1_IRQHandler,Default_Handler
+
+    .weak   SAI2_IRQHandler
+    .thumb_set SAI2_IRQHandler,Default_Handler
+
+    .weak   OCTOSPI2_IRQHandler
+    .thumb_set OCTOSPI2_IRQHandler,Default_Handler
+
+    .weak   TSC_IRQHandler
+    .thumb_set TSC_IRQHandler,Default_Handler
+
+    .weak   DSI_IRQHandler
+    .thumb_set DSI_IRQHandler,Default_Handler
+
+    .weak   RNG_IRQHandler
+    .thumb_set RNG_IRQHandler,Default_Handler
+
+    .weak   FPU_IRQHandler
+    .thumb_set FPU_IRQHandler,Default_Handler
+
+    .weak   CRS_IRQHandler
+    .thumb_set CRS_IRQHandler,Default_Handler
+
+    .weak   I2C4_ER_IRQHandler
+    .thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+    .weak   I2C4_EV_IRQHandler
+    .thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+    .weak   DCMI_IRQHandler
+    .thumb_set DCMI_IRQHandler,Default_Handler
+
+    .weak   DMA2D_IRQHandler
+    .thumb_set DMA2D_IRQHandler,Default_Handler
+
+    .weak   LTDC_IRQHandler
+    .thumb_set LTDC_IRQHandler,Default_Handler
+
+    .weak   LTDC_ER_IRQHandler
+    .thumb_set LTDC_ER_IRQHandler,Default_Handler
+
+    .weak   GFXMMU_IRQHandler
+    .thumb_set GFXMMU_IRQHandler,Default_Handler
+
+    .weak   DMAMUX1_OVR_IRQHandler
+    .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

CMSIS/STM32L4xx/Source/Templates/gcc/startup_stm32l4s5xx.s

@@ -0,0 +1,546 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32l4s5xx.s
+  * @author    MCD Application Team
+  * @brief     STM32L4S5xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address,
+  *                - Configure the clock system
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Apache License, Version 2.0,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/Apache-2.0
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+    .cpu cortex-m4
+    .fpu softvfp
+    .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word   _sidata
+/* start address for the .data section. defined in linker script */
+.word   _sdata
+/* end address for the .data section. defined in linker script */
+.word   _edata
+/* start address for the .bss section. defined in linker script */
+.word   _sbss
+/* end address for the .bss section. defined in linker script */
+.word   _ebss
+
+.equ  BootRAM,        0xF1E0F85F
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+    .section    .text.Reset_Handler
+    .weak   Reset_Handler
+    .type   Reset_Handler, %function
+Reset_Handler:
+  ldr   sp, =_estack    /* Set stack pointer */
+
+/* Call the clock system initialization function.*/
+    bl  SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b LoopCopyDataInit
+
+CopyDataInit:
+    ldr r3, =_sidata
+    ldr r3, [r3, r1]
+    str r3, [r0, r1]
+    adds    r1, r1, #4
+
+LoopCopyDataInit:
+    ldr r0, =_sdata
+    ldr r3, =_edata
+    adds    r2, r0, r1
+    cmp r2, r3
+    bcc CopyDataInit
+    ldr r2, =_sbss
+    b   LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+    movs    r3, #0
+    str r3, [r2], #4
+
+LoopFillZerobss:
+    ldr r3, = _ebss
+    cmp r2, r3
+    bcc FillZerobss
+
+/* Call static constructors */
+    bl __libc_init_array
+/* Call the application's entry point.*/
+    bl  main
+
+LoopForever:
+    b LoopForever
+
+.size   Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section    .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+    b   Infinite_Loop
+    .size   Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+    .section    .isr_vector,"a",%progbits
+    .type   g_pfnVectors, %object
+    .size   g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+    .word   _estack
+    .word   Reset_Handler
+    .word   NMI_Handler
+    .word   HardFault_Handler
+    .word   MemManage_Handler
+    .word   BusFault_Handler
+    .word   UsageFault_Handler
+    .word   0
+    .word   0
+    .word   0
+    .word   0
+    .word   SVC_Handler
+    .word   DebugMon_Handler
+    .word   0
+    .word   PendSV_Handler
+    .word   SysTick_Handler
+    .word   WWDG_IRQHandler
+    .word   PVD_PVM_IRQHandler
+    .word   TAMP_STAMP_IRQHandler
+    .word   RTC_WKUP_IRQHandler
+    .word   FLASH_IRQHandler
+    .word   RCC_IRQHandler
+    .word   EXTI0_IRQHandler
+    .word   EXTI1_IRQHandler
+    .word   EXTI2_IRQHandler
+    .word   EXTI3_IRQHandler
+    .word   EXTI4_IRQHandler
+    .word   DMA1_Channel1_IRQHandler
+    .word   DMA1_Channel2_IRQHandler
+    .word   DMA1_Channel3_IRQHandler
+    .word   DMA1_Channel4_IRQHandler
+    .word   DMA1_Channel5_IRQHandler
+    .word   DMA1_Channel6_IRQHandler
+    .word   DMA1_Channel7_IRQHandler
+    .word   ADC1_IRQHandler
+    .word   CAN1_TX_IRQHandler
+    .word   CAN1_RX0_IRQHandler
+    .word   CAN1_RX1_IRQHandler
+    .word   CAN1_SCE_IRQHandler
+    .word   EXTI9_5_IRQHandler
+    .word   TIM1_BRK_TIM15_IRQHandler
+    .word   TIM1_UP_TIM16_IRQHandler
+    .word   TIM1_TRG_COM_TIM17_IRQHandler
+    .word   TIM1_CC_IRQHandler
+    .word   TIM2_IRQHandler
+    .word   TIM3_IRQHandler
+    .word   TIM4_IRQHandler
+    .word   I2C1_EV_IRQHandler
+    .word   I2C1_ER_IRQHandler
+    .word   I2C2_EV_IRQHandler
+    .word   I2C2_ER_IRQHandler
+    .word   SPI1_IRQHandler
+    .word   SPI2_IRQHandler
+    .word   USART1_IRQHandler
+    .word   USART2_IRQHandler
+    .word   USART3_IRQHandler
+    .word   EXTI15_10_IRQHandler
+    .word   RTC_Alarm_IRQHandler
+    .word   DFSDM1_FLT3_IRQHandler
+    .word   TIM8_BRK_IRQHandler
+    .word   TIM8_UP_IRQHandler
+    .word   TIM8_TRG_COM_IRQHandler
+    .word   TIM8_CC_IRQHandler
+    .word   0
+    .word   FMC_IRQHandler
+    .word   SDMMC1_IRQHandler
+    .word   TIM5_IRQHandler
+    .word   SPI3_IRQHandler
+    .word   UART4_IRQHandler
+    .word   UART5_IRQHandler
+    .word   TIM6_DAC_IRQHandler
+    .word   TIM7_IRQHandler
+    .word   DMA2_Channel1_IRQHandler
+    .word   DMA2_Channel2_IRQHandler
+    .word   DMA2_Channel3_IRQHandler
+    .word   DMA2_Channel4_IRQHandler
+    .word   DMA2_Channel5_IRQHandler
+    .word   DFSDM1_FLT0_IRQHandler
+    .word   DFSDM1_FLT1_IRQHandler
+    .word   DFSDM1_FLT2_IRQHandler
+    .word   COMP_IRQHandler
+    .word   LPTIM1_IRQHandler
+    .word   LPTIM2_IRQHandler
+    .word   OTG_FS_IRQHandler
+    .word   DMA2_Channel6_IRQHandler
+    .word   DMA2_Channel7_IRQHandler
+    .word   LPUART1_IRQHandler
+    .word   OCTOSPI1_IRQHandler
+    .word   I2C3_EV_IRQHandler
+    .word   I2C3_ER_IRQHandler
+    .word   SAI1_IRQHandler
+    .word   SAI2_IRQHandler
+    .word   OCTOSPI2_IRQHandler
+    .word   TSC_IRQHandler
+    .word   0
+    .word   AES_IRQHandler
+    .word   RNG_IRQHandler
+    .word   FPU_IRQHandler
+    .word   HASH_CRS_IRQHandler
+    .word   I2C4_ER_IRQHandler
+    .word   I2C4_EV_IRQHandler
+    .word   DCMI_IRQHandler
+    .word   0
+    .word   0
+    .word   0
+    .word   0
+    .word   DMA2D_IRQHandler
+    .word   LTDC_IRQHandler
+    .word   LTDC_ER_IRQHandler
+    .word   GFXMMU_IRQHandler
+    .word   DMAMUX1_OVR_IRQHandler
+
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+  .weak NMI_Handler
+    .thumb_set NMI_Handler,Default_Handler
+
+  .weak HardFault_Handler
+    .thumb_set HardFault_Handler,Default_Handler
+
+  .weak MemManage_Handler
+    .thumb_set MemManage_Handler,Default_Handler
+
+  .weak BusFault_Handler
+    .thumb_set BusFault_Handler,Default_Handler
+
+    .weak   UsageFault_Handler
+    .thumb_set UsageFault_Handler,Default_Handler
+
+    .weak   SVC_Handler
+    .thumb_set SVC_Handler,Default_Handler
+
+    .weak   DebugMon_Handler
+    .thumb_set DebugMon_Handler,Default_Handler
+
+    .weak   PendSV_Handler
+    .thumb_set PendSV_Handler,Default_Handler
+
+    .weak   SysTick_Handler
+    .thumb_set SysTick_Handler,Default_Handler
+
+    .weak   WWDG_IRQHandler
+    .thumb_set WWDG_IRQHandler,Default_Handler
+
+    .weak   PVD_PVM_IRQHandler
+    .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+    .weak   TAMP_STAMP_IRQHandler
+    .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+    .weak   RTC_WKUP_IRQHandler
+    .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+    .weak   FLASH_IRQHandler
+    .thumb_set FLASH_IRQHandler,Default_Handler
+
+    .weak   RCC_IRQHandler
+    .thumb_set RCC_IRQHandler,Default_Handler
+
+    .weak   EXTI0_IRQHandler
+    .thumb_set EXTI0_IRQHandler,Default_Handler
+
+    .weak   EXTI1_IRQHandler
+    .thumb_set EXTI1_IRQHandler,Default_Handler
+
+    .weak   EXTI2_IRQHandler
+    .thumb_set EXTI2_IRQHandler,Default_Handler
+
+    .weak   EXTI3_IRQHandler
+    .thumb_set EXTI3_IRQHandler,Default_Handler
+
+    .weak   EXTI4_IRQHandler
+    .thumb_set EXTI4_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel1_IRQHandler
+    .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel2_IRQHandler
+    .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel3_IRQHandler
+    .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel4_IRQHandler
+    .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel5_IRQHandler
+    .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel6_IRQHandler
+    .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel7_IRQHandler
+    .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+    .weak   ADC1_IRQHandler
+    .thumb_set ADC1_IRQHandler,Default_Handler
+
+    .weak   CAN1_TX_IRQHandler
+    .thumb_set CAN1_TX_IRQHandler,Default_Handler
+
+    .weak   CAN1_RX0_IRQHandler
+    .thumb_set CAN1_RX0_IRQHandler,Default_Handler
+
+    .weak   CAN1_RX1_IRQHandler
+    .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+    .weak   CAN1_SCE_IRQHandler
+    .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+    .weak   EXTI9_5_IRQHandler
+    .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+    .weak   TIM1_BRK_TIM15_IRQHandler
+    .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+    .weak   TIM1_UP_TIM16_IRQHandler
+    .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+    .weak   TIM1_TRG_COM_TIM17_IRQHandler
+    .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+    .weak   TIM1_CC_IRQHandler
+    .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+    .weak   TIM2_IRQHandler
+    .thumb_set TIM2_IRQHandler,Default_Handler
+
+    .weak   TIM3_IRQHandler
+    .thumb_set TIM3_IRQHandler,Default_Handler
+
+    .weak   TIM4_IRQHandler
+    .thumb_set TIM4_IRQHandler,Default_Handler
+
+    .weak   I2C1_EV_IRQHandler
+    .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+    .weak   I2C1_ER_IRQHandler
+    .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+    .weak   I2C2_EV_IRQHandler
+    .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+    .weak   I2C2_ER_IRQHandler
+    .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+    .weak   SPI1_IRQHandler
+    .thumb_set SPI1_IRQHandler,Default_Handler
+
+    .weak   SPI2_IRQHandler
+    .thumb_set SPI2_IRQHandler,Default_Handler
+
+    .weak   USART1_IRQHandler
+    .thumb_set USART1_IRQHandler,Default_Handler
+
+    .weak   USART2_IRQHandler
+    .thumb_set USART2_IRQHandler,Default_Handler
+
+    .weak   USART3_IRQHandler
+    .thumb_set USART3_IRQHandler,Default_Handler
+
+    .weak   EXTI15_10_IRQHandler
+    .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+    .weak   RTC_Alarm_IRQHandler
+    .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+    .weak   DFSDM1_FLT3_IRQHandler
+    .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+
+    .weak   TIM8_BRK_IRQHandler
+    .thumb_set TIM8_BRK_IRQHandler,Default_Handler
+
+    .weak   TIM8_UP_IRQHandler
+    .thumb_set TIM8_UP_IRQHandler,Default_Handler
+
+    .weak   TIM8_TRG_COM_IRQHandler
+    .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+
+    .weak   TIM8_CC_IRQHandler
+    .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+    .weak   FMC_IRQHandler
+    .thumb_set FMC_IRQHandler,Default_Handler
+
+    .weak   SDMMC1_IRQHandler
+    .thumb_set SDMMC1_IRQHandler,Default_Handler
+
+    .weak   TIM5_IRQHandler
+    .thumb_set TIM5_IRQHandler,Default_Handler
+
+    .weak   SPI3_IRQHandler
+    .thumb_set SPI3_IRQHandler,Default_Handler
+
+    .weak   UART4_IRQHandler
+    .thumb_set UART4_IRQHandler,Default_Handler
+
+    .weak   UART5_IRQHandler
+    .thumb_set UART5_IRQHandler,Default_Handler
+
+    .weak   TIM6_DAC_IRQHandler
+    .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+    .weak   TIM7_IRQHandler
+    .thumb_set TIM7_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel1_IRQHandler
+    .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel2_IRQHandler
+    .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel3_IRQHandler
+    .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel4_IRQHandler
+    .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel5_IRQHandler
+    .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+    .weak   DFSDM1_FLT0_IRQHandler
+    .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+
+    .weak   DFSDM1_FLT1_IRQHandler
+    .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+
+    .weak   DFSDM1_FLT2_IRQHandler
+    .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+
+    .weak   COMP_IRQHandler
+    .thumb_set COMP_IRQHandler,Default_Handler
+
+    .weak   LPTIM1_IRQHandler
+    .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+    .weak   LPTIM2_IRQHandler
+    .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+    .weak   OTG_FS_IRQHandler
+    .thumb_set OTG_FS_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel6_IRQHandler
+    .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel7_IRQHandler
+    .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+    .weak   LPUART1_IRQHandler
+    .thumb_set LPUART1_IRQHandler,Default_Handler
+
+    .weak   OCTOSPI1_IRQHandler
+    .thumb_set OCTOSPI1_IRQHandler,Default_Handler
+
+    .weak   I2C3_EV_IRQHandler
+    .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+    .weak   I2C3_ER_IRQHandler
+    .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+    .weak   SAI1_IRQHandler
+    .thumb_set SAI1_IRQHandler,Default_Handler
+
+    .weak   SAI2_IRQHandler
+    .thumb_set SAI2_IRQHandler,Default_Handler
+
+    .weak   OCTOSPI2_IRQHandler
+    .thumb_set OCTOSPI2_IRQHandler,Default_Handler
+
+    .weak   TSC_IRQHandler
+    .thumb_set TSC_IRQHandler,Default_Handler
+
+    .weak   AES_IRQHandler
+    .thumb_set AES_IRQHandler,Default_Handler
+
+    .weak   RNG_IRQHandler
+    .thumb_set RNG_IRQHandler,Default_Handler
+
+    .weak   FPU_IRQHandler
+    .thumb_set FPU_IRQHandler,Default_Handler
+
+    .weak   HASH_CRS_IRQHandler
+    .thumb_set HASH_CRS_IRQHandler,Default_Handler
+
+    .weak   I2C4_ER_IRQHandler
+    .thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+    .weak   I2C4_EV_IRQHandler
+    .thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+    .weak   DCMI_IRQHandler
+    .thumb_set DCMI_IRQHandler,Default_Handler
+
+    .weak   DMA2D_IRQHandler
+    .thumb_set DMA2D_IRQHandler,Default_Handler
+
+    .weak   LTDC_IRQHandler
+    .thumb_set LTDC_IRQHandler,Default_Handler
+
+    .weak   LTDC_ER_IRQHandler
+    .thumb_set LTDC_ER_IRQHandler,Default_Handler
+
+    .weak   GFXMMU_IRQHandler
+    .thumb_set GFXMMU_IRQHandler,Default_Handler
+
+    .weak   DMAMUX1_OVR_IRQHandler
+    .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

CMSIS/STM32L4xx/Source/Templates/gcc/startup_stm32l4s7xx.s

@@ -0,0 +1,546 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32l4s7xx.s
+  * @author    MCD Application Team
+  * @brief     STM32L4S7xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address,
+  *                - Configure the clock system
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Apache License, Version 2.0,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/Apache-2.0
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+    .cpu cortex-m4
+    .fpu softvfp
+    .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word   _sidata
+/* start address for the .data section. defined in linker script */
+.word   _sdata
+/* end address for the .data section. defined in linker script */
+.word   _edata
+/* start address for the .bss section. defined in linker script */
+.word   _sbss
+/* end address for the .bss section. defined in linker script */
+.word   _ebss
+
+.equ  BootRAM,        0xF1E0F85F
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+    .section    .text.Reset_Handler
+    .weak   Reset_Handler
+    .type   Reset_Handler, %function
+Reset_Handler:
+  ldr   sp, =_estack    /* Set stack pointer */
+
+/* Call the clock system initialization function.*/
+    bl  SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b LoopCopyDataInit
+
+CopyDataInit:
+    ldr r3, =_sidata
+    ldr r3, [r3, r1]
+    str r3, [r0, r1]
+    adds    r1, r1, #4
+
+LoopCopyDataInit:
+    ldr r0, =_sdata
+    ldr r3, =_edata
+    adds    r2, r0, r1
+    cmp r2, r3
+    bcc CopyDataInit
+    ldr r2, =_sbss
+    b   LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+    movs    r3, #0
+    str r3, [r2], #4
+
+LoopFillZerobss:
+    ldr r3, = _ebss
+    cmp r2, r3
+    bcc FillZerobss
+
+/* Call static constructors */
+    bl __libc_init_array
+/* Call the application's entry point.*/
+    bl  main
+
+LoopForever:
+    b LoopForever
+
+.size   Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section    .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+    b   Infinite_Loop
+    .size   Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+    .section    .isr_vector,"a",%progbits
+    .type   g_pfnVectors, %object
+    .size   g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+    .word   _estack
+    .word   Reset_Handler
+    .word   NMI_Handler
+    .word   HardFault_Handler
+    .word   MemManage_Handler
+    .word   BusFault_Handler
+    .word   UsageFault_Handler
+    .word   0
+    .word   0
+    .word   0
+    .word   0
+    .word   SVC_Handler
+    .word   DebugMon_Handler
+    .word   0
+    .word   PendSV_Handler
+    .word   SysTick_Handler
+    .word   WWDG_IRQHandler
+    .word   PVD_PVM_IRQHandler
+    .word   TAMP_STAMP_IRQHandler
+    .word   RTC_WKUP_IRQHandler
+    .word   FLASH_IRQHandler
+    .word   RCC_IRQHandler
+    .word   EXTI0_IRQHandler
+    .word   EXTI1_IRQHandler
+    .word   EXTI2_IRQHandler
+    .word   EXTI3_IRQHandler
+    .word   EXTI4_IRQHandler
+    .word   DMA1_Channel1_IRQHandler
+    .word   DMA1_Channel2_IRQHandler
+    .word   DMA1_Channel3_IRQHandler
+    .word   DMA1_Channel4_IRQHandler
+    .word   DMA1_Channel5_IRQHandler
+    .word   DMA1_Channel6_IRQHandler
+    .word   DMA1_Channel7_IRQHandler
+    .word   ADC1_IRQHandler
+    .word   CAN1_TX_IRQHandler
+    .word   CAN1_RX0_IRQHandler
+    .word   CAN1_RX1_IRQHandler
+    .word   CAN1_SCE_IRQHandler
+    .word   EXTI9_5_IRQHandler
+    .word   TIM1_BRK_TIM15_IRQHandler
+    .word   TIM1_UP_TIM16_IRQHandler
+    .word   TIM1_TRG_COM_TIM17_IRQHandler
+    .word   TIM1_CC_IRQHandler
+    .word   TIM2_IRQHandler
+    .word   TIM3_IRQHandler
+    .word   TIM4_IRQHandler
+    .word   I2C1_EV_IRQHandler
+    .word   I2C1_ER_IRQHandler
+    .word   I2C2_EV_IRQHandler
+    .word   I2C2_ER_IRQHandler
+    .word   SPI1_IRQHandler
+    .word   SPI2_IRQHandler
+    .word   USART1_IRQHandler
+    .word   USART2_IRQHandler
+    .word   USART3_IRQHandler
+    .word   EXTI15_10_IRQHandler
+    .word   RTC_Alarm_IRQHandler
+    .word   DFSDM1_FLT3_IRQHandler
+    .word   TIM8_BRK_IRQHandler
+    .word   TIM8_UP_IRQHandler
+    .word   TIM8_TRG_COM_IRQHandler
+    .word   TIM8_CC_IRQHandler
+    .word   0
+    .word   FMC_IRQHandler
+    .word   SDMMC1_IRQHandler
+    .word   TIM5_IRQHandler
+    .word   SPI3_IRQHandler
+    .word   UART4_IRQHandler
+    .word   UART5_IRQHandler
+    .word   TIM6_DAC_IRQHandler
+    .word   TIM7_IRQHandler
+    .word   DMA2_Channel1_IRQHandler
+    .word   DMA2_Channel2_IRQHandler
+    .word   DMA2_Channel3_IRQHandler
+    .word   DMA2_Channel4_IRQHandler
+    .word   DMA2_Channel5_IRQHandler
+    .word   DFSDM1_FLT0_IRQHandler
+    .word   DFSDM1_FLT1_IRQHandler
+    .word   DFSDM1_FLT2_IRQHandler
+    .word   COMP_IRQHandler
+    .word   LPTIM1_IRQHandler
+    .word   LPTIM2_IRQHandler
+    .word   OTG_FS_IRQHandler
+    .word   DMA2_Channel6_IRQHandler
+    .word   DMA2_Channel7_IRQHandler
+    .word   LPUART1_IRQHandler
+    .word   OCTOSPI1_IRQHandler
+    .word   I2C3_EV_IRQHandler
+    .word   I2C3_ER_IRQHandler
+    .word   SAI1_IRQHandler
+    .word   SAI2_IRQHandler
+    .word   OCTOSPI2_IRQHandler
+    .word   TSC_IRQHandler
+    .word   0
+    .word   AES_IRQHandler
+    .word   RNG_IRQHandler
+    .word   FPU_IRQHandler
+    .word   HASH_CRS_IRQHandler
+    .word   I2C4_ER_IRQHandler
+    .word   I2C4_EV_IRQHandler
+    .word   DCMI_IRQHandler
+    .word   0
+    .word   0
+    .word   0
+    .word   0
+    .word   DMA2D_IRQHandler
+    .word   LTDC_IRQHandler
+    .word   LTDC_ER_IRQHandler
+    .word   GFXMMU_IRQHandler
+    .word   DMAMUX1_OVR_IRQHandler
+
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+  .weak NMI_Handler
+    .thumb_set NMI_Handler,Default_Handler
+
+  .weak HardFault_Handler
+    .thumb_set HardFault_Handler,Default_Handler
+
+  .weak MemManage_Handler
+    .thumb_set MemManage_Handler,Default_Handler
+
+  .weak BusFault_Handler
+    .thumb_set BusFault_Handler,Default_Handler
+
+    .weak   UsageFault_Handler
+    .thumb_set UsageFault_Handler,Default_Handler
+
+    .weak   SVC_Handler
+    .thumb_set SVC_Handler,Default_Handler
+
+    .weak   DebugMon_Handler
+    .thumb_set DebugMon_Handler,Default_Handler
+
+    .weak   PendSV_Handler
+    .thumb_set PendSV_Handler,Default_Handler
+
+    .weak   SysTick_Handler
+    .thumb_set SysTick_Handler,Default_Handler
+
+    .weak   WWDG_IRQHandler
+    .thumb_set WWDG_IRQHandler,Default_Handler
+
+    .weak   PVD_PVM_IRQHandler
+    .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+    .weak   TAMP_STAMP_IRQHandler
+    .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+    .weak   RTC_WKUP_IRQHandler
+    .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+    .weak   FLASH_IRQHandler
+    .thumb_set FLASH_IRQHandler,Default_Handler
+
+    .weak   RCC_IRQHandler
+    .thumb_set RCC_IRQHandler,Default_Handler
+
+    .weak   EXTI0_IRQHandler
+    .thumb_set EXTI0_IRQHandler,Default_Handler
+
+    .weak   EXTI1_IRQHandler
+    .thumb_set EXTI1_IRQHandler,Default_Handler
+
+    .weak   EXTI2_IRQHandler
+    .thumb_set EXTI2_IRQHandler,Default_Handler
+
+    .weak   EXTI3_IRQHandler
+    .thumb_set EXTI3_IRQHandler,Default_Handler
+
+    .weak   EXTI4_IRQHandler
+    .thumb_set EXTI4_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel1_IRQHandler
+    .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel2_IRQHandler
+    .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel3_IRQHandler
+    .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel4_IRQHandler
+    .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel5_IRQHandler
+    .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel6_IRQHandler
+    .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel7_IRQHandler
+    .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+    .weak   ADC1_IRQHandler
+    .thumb_set ADC1_IRQHandler,Default_Handler
+
+    .weak   CAN1_TX_IRQHandler
+    .thumb_set CAN1_TX_IRQHandler,Default_Handler
+
+    .weak   CAN1_RX0_IRQHandler
+    .thumb_set CAN1_RX0_IRQHandler,Default_Handler
+
+    .weak   CAN1_RX1_IRQHandler
+    .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+    .weak   CAN1_SCE_IRQHandler
+    .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+    .weak   EXTI9_5_IRQHandler
+    .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+    .weak   TIM1_BRK_TIM15_IRQHandler
+    .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+    .weak   TIM1_UP_TIM16_IRQHandler
+    .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+    .weak   TIM1_TRG_COM_TIM17_IRQHandler
+    .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+    .weak   TIM1_CC_IRQHandler
+    .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+    .weak   TIM2_IRQHandler
+    .thumb_set TIM2_IRQHandler,Default_Handler
+
+    .weak   TIM3_IRQHandler
+    .thumb_set TIM3_IRQHandler,Default_Handler
+
+    .weak   TIM4_IRQHandler
+    .thumb_set TIM4_IRQHandler,Default_Handler
+
+    .weak   I2C1_EV_IRQHandler
+    .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+    .weak   I2C1_ER_IRQHandler
+    .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+    .weak   I2C2_EV_IRQHandler
+    .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+    .weak   I2C2_ER_IRQHandler
+    .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+    .weak   SPI1_IRQHandler
+    .thumb_set SPI1_IRQHandler,Default_Handler
+
+    .weak   SPI2_IRQHandler
+    .thumb_set SPI2_IRQHandler,Default_Handler
+
+    .weak   USART1_IRQHandler
+    .thumb_set USART1_IRQHandler,Default_Handler
+
+    .weak   USART2_IRQHandler
+    .thumb_set USART2_IRQHandler,Default_Handler
+
+    .weak   USART3_IRQHandler
+    .thumb_set USART3_IRQHandler,Default_Handler
+
+    .weak   EXTI15_10_IRQHandler
+    .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+    .weak   RTC_Alarm_IRQHandler
+    .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+    .weak   DFSDM1_FLT3_IRQHandler
+    .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+
+    .weak   TIM8_BRK_IRQHandler
+    .thumb_set TIM8_BRK_IRQHandler,Default_Handler
+
+    .weak   TIM8_UP_IRQHandler
+    .thumb_set TIM8_UP_IRQHandler,Default_Handler
+
+    .weak   TIM8_TRG_COM_IRQHandler
+    .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+
+    .weak   TIM8_CC_IRQHandler
+    .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+    .weak   FMC_IRQHandler
+    .thumb_set FMC_IRQHandler,Default_Handler
+
+    .weak   SDMMC1_IRQHandler
+    .thumb_set SDMMC1_IRQHandler,Default_Handler
+
+    .weak   TIM5_IRQHandler
+    .thumb_set TIM5_IRQHandler,Default_Handler
+
+    .weak   SPI3_IRQHandler
+    .thumb_set SPI3_IRQHandler,Default_Handler
+
+    .weak   UART4_IRQHandler
+    .thumb_set UART4_IRQHandler,Default_Handler
+
+    .weak   UART5_IRQHandler
+    .thumb_set UART5_IRQHandler,Default_Handler
+
+    .weak   TIM6_DAC_IRQHandler
+    .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+    .weak   TIM7_IRQHandler
+    .thumb_set TIM7_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel1_IRQHandler
+    .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel2_IRQHandler
+    .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel3_IRQHandler
+    .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel4_IRQHandler
+    .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel5_IRQHandler
+    .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+    .weak   DFSDM1_FLT0_IRQHandler
+    .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+
+    .weak   DFSDM1_FLT1_IRQHandler
+    .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+
+    .weak   DFSDM1_FLT2_IRQHandler
+    .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+
+    .weak   COMP_IRQHandler
+    .thumb_set COMP_IRQHandler,Default_Handler
+
+    .weak   LPTIM1_IRQHandler
+    .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+    .weak   LPTIM2_IRQHandler
+    .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+    .weak   OTG_FS_IRQHandler
+    .thumb_set OTG_FS_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel6_IRQHandler
+    .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel7_IRQHandler
+    .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+    .weak   LPUART1_IRQHandler
+    .thumb_set LPUART1_IRQHandler,Default_Handler
+
+    .weak   OCTOSPI1_IRQHandler
+    .thumb_set OCTOSPI1_IRQHandler,Default_Handler
+
+    .weak   I2C3_EV_IRQHandler
+    .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+    .weak   I2C3_ER_IRQHandler
+    .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+    .weak   SAI1_IRQHandler
+    .thumb_set SAI1_IRQHandler,Default_Handler
+
+    .weak   SAI2_IRQHandler
+    .thumb_set SAI2_IRQHandler,Default_Handler
+
+    .weak   OCTOSPI2_IRQHandler
+    .thumb_set OCTOSPI2_IRQHandler,Default_Handler
+
+    .weak   TSC_IRQHandler
+    .thumb_set TSC_IRQHandler,Default_Handler
+
+    .weak   AES_IRQHandler
+    .thumb_set AES_IRQHandler,Default_Handler
+
+    .weak   RNG_IRQHandler
+    .thumb_set RNG_IRQHandler,Default_Handler
+
+    .weak   FPU_IRQHandler
+    .thumb_set FPU_IRQHandler,Default_Handler
+
+    .weak   HASH_CRS_IRQHandler
+    .thumb_set HASH_CRS_IRQHandler,Default_Handler
+
+    .weak   I2C4_ER_IRQHandler
+    .thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+    .weak   I2C4_EV_IRQHandler
+    .thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+    .weak   DCMI_IRQHandler
+    .thumb_set DCMI_IRQHandler,Default_Handler
+
+    .weak   DMA2D_IRQHandler
+    .thumb_set DMA2D_IRQHandler,Default_Handler
+
+    .weak   LTDC_IRQHandler
+    .thumb_set LTDC_IRQHandler,Default_Handler
+
+    .weak   LTDC_ER_IRQHandler
+    .thumb_set LTDC_ER_IRQHandler,Default_Handler
+
+    .weak   GFXMMU_IRQHandler
+    .thumb_set GFXMMU_IRQHandler,Default_Handler
+
+    .weak   DMAMUX1_OVR_IRQHandler
+    .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

CMSIS/STM32L4xx/Source/Templates/gcc/startup_stm32l4s9xx.s

@@ -0,0 +1,549 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32l4s9xx.s
+  * @author    MCD Application Team
+  * @brief     STM32L4S9xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address,
+  *                - Configure the clock system
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Apache License, Version 2.0,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/Apache-2.0
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+    .cpu cortex-m4
+    .fpu softvfp
+    .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word   _sidata
+/* start address for the .data section. defined in linker script */
+.word   _sdata
+/* end address for the .data section. defined in linker script */
+.word   _edata
+/* start address for the .bss section. defined in linker script */
+.word   _sbss
+/* end address for the .bss section. defined in linker script */
+.word   _ebss
+
+.equ  BootRAM,        0xF1E0F85F
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+    .section    .text.Reset_Handler
+    .weak   Reset_Handler
+    .type   Reset_Handler, %function
+Reset_Handler:
+  ldr   sp, =_estack    /* Set stack pointer */
+
+/* Call the clock system initialization function.*/
+    bl  SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b LoopCopyDataInit
+
+CopyDataInit:
+    ldr r3, =_sidata
+    ldr r3, [r3, r1]
+    str r3, [r0, r1]
+    adds    r1, r1, #4
+
+LoopCopyDataInit:
+    ldr r0, =_sdata
+    ldr r3, =_edata
+    adds    r2, r0, r1
+    cmp r2, r3
+    bcc CopyDataInit
+    ldr r2, =_sbss
+    b   LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+    movs    r3, #0
+    str r3, [r2], #4
+
+LoopFillZerobss:
+    ldr r3, = _ebss
+    cmp r2, r3
+    bcc FillZerobss
+
+/* Call static constructors */
+    bl __libc_init_array
+/* Call the application's entry point.*/
+    bl  main
+
+LoopForever:
+    b LoopForever
+
+.size   Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section    .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+    b   Infinite_Loop
+    .size   Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+    .section    .isr_vector,"a",%progbits
+    .type   g_pfnVectors, %object
+    .size   g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+    .word   _estack
+    .word   Reset_Handler
+    .word   NMI_Handler
+    .word   HardFault_Handler
+    .word   MemManage_Handler
+    .word   BusFault_Handler
+    .word   UsageFault_Handler
+    .word   0
+    .word   0
+    .word   0
+    .word   0
+    .word   SVC_Handler
+    .word   DebugMon_Handler
+    .word   0
+    .word   PendSV_Handler
+    .word   SysTick_Handler
+    .word   WWDG_IRQHandler
+    .word   PVD_PVM_IRQHandler
+    .word   TAMP_STAMP_IRQHandler
+    .word   RTC_WKUP_IRQHandler
+    .word   FLASH_IRQHandler
+    .word   RCC_IRQHandler
+    .word   EXTI0_IRQHandler
+    .word   EXTI1_IRQHandler
+    .word   EXTI2_IRQHandler
+    .word   EXTI3_IRQHandler
+    .word   EXTI4_IRQHandler
+    .word   DMA1_Channel1_IRQHandler
+    .word   DMA1_Channel2_IRQHandler
+    .word   DMA1_Channel3_IRQHandler
+    .word   DMA1_Channel4_IRQHandler
+    .word   DMA1_Channel5_IRQHandler
+    .word   DMA1_Channel6_IRQHandler
+    .word   DMA1_Channel7_IRQHandler
+    .word   ADC1_IRQHandler
+    .word   CAN1_TX_IRQHandler
+    .word   CAN1_RX0_IRQHandler
+    .word   CAN1_RX1_IRQHandler
+    .word   CAN1_SCE_IRQHandler
+    .word   EXTI9_5_IRQHandler
+    .word   TIM1_BRK_TIM15_IRQHandler
+    .word   TIM1_UP_TIM16_IRQHandler
+    .word   TIM1_TRG_COM_TIM17_IRQHandler
+    .word   TIM1_CC_IRQHandler
+    .word   TIM2_IRQHandler
+    .word   TIM3_IRQHandler
+    .word   TIM4_IRQHandler
+    .word   I2C1_EV_IRQHandler
+    .word   I2C1_ER_IRQHandler
+    .word   I2C2_EV_IRQHandler
+    .word   I2C2_ER_IRQHandler
+    .word   SPI1_IRQHandler
+    .word   SPI2_IRQHandler
+    .word   USART1_IRQHandler
+    .word   USART2_IRQHandler
+    .word   USART3_IRQHandler
+    .word   EXTI15_10_IRQHandler
+    .word   RTC_Alarm_IRQHandler
+    .word   DFSDM1_FLT3_IRQHandler
+    .word   TIM8_BRK_IRQHandler
+    .word   TIM8_UP_IRQHandler
+    .word   TIM8_TRG_COM_IRQHandler
+    .word   TIM8_CC_IRQHandler
+    .word   0
+    .word   FMC_IRQHandler
+    .word   SDMMC1_IRQHandler
+    .word   TIM5_IRQHandler
+    .word   SPI3_IRQHandler
+    .word   UART4_IRQHandler
+    .word   UART5_IRQHandler
+    .word   TIM6_DAC_IRQHandler
+    .word   TIM7_IRQHandler
+    .word   DMA2_Channel1_IRQHandler
+    .word   DMA2_Channel2_IRQHandler
+    .word   DMA2_Channel3_IRQHandler
+    .word   DMA2_Channel4_IRQHandler
+    .word   DMA2_Channel5_IRQHandler
+    .word   DFSDM1_FLT0_IRQHandler
+    .word   DFSDM1_FLT1_IRQHandler
+    .word   DFSDM1_FLT2_IRQHandler
+    .word   COMP_IRQHandler
+    .word   LPTIM1_IRQHandler
+    .word   LPTIM2_IRQHandler
+    .word   OTG_FS_IRQHandler
+    .word   DMA2_Channel6_IRQHandler
+    .word   DMA2_Channel7_IRQHandler
+    .word   LPUART1_IRQHandler
+    .word   OCTOSPI1_IRQHandler
+    .word   I2C3_EV_IRQHandler
+    .word   I2C3_ER_IRQHandler
+    .word   SAI1_IRQHandler
+    .word   SAI2_IRQHandler
+    .word   OCTOSPI2_IRQHandler
+    .word   TSC_IRQHandler
+    .word   DSI_IRQHandler
+    .word   AES_IRQHandler
+    .word   RNG_IRQHandler
+    .word   FPU_IRQHandler
+    .word   HASH_CRS_IRQHandler
+    .word   I2C4_ER_IRQHandler
+    .word   I2C4_EV_IRQHandler
+    .word   DCMI_IRQHandler
+    .word   0
+    .word   0
+    .word   0
+    .word   0
+    .word   DMA2D_IRQHandler
+    .word   LTDC_IRQHandler
+    .word   LTDC_ER_IRQHandler
+    .word   GFXMMU_IRQHandler
+    .word   DMAMUX1_OVR_IRQHandler
+
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+  .weak NMI_Handler
+    .thumb_set NMI_Handler,Default_Handler
+
+  .weak HardFault_Handler
+    .thumb_set HardFault_Handler,Default_Handler
+
+  .weak MemManage_Handler
+    .thumb_set MemManage_Handler,Default_Handler
+
+  .weak BusFault_Handler
+    .thumb_set BusFault_Handler,Default_Handler
+
+    .weak   UsageFault_Handler
+    .thumb_set UsageFault_Handler,Default_Handler
+
+    .weak   SVC_Handler
+    .thumb_set SVC_Handler,Default_Handler
+
+    .weak   DebugMon_Handler
+    .thumb_set DebugMon_Handler,Default_Handler
+
+    .weak   PendSV_Handler
+    .thumb_set PendSV_Handler,Default_Handler
+
+    .weak   SysTick_Handler
+    .thumb_set SysTick_Handler,Default_Handler
+
+    .weak   WWDG_IRQHandler
+    .thumb_set WWDG_IRQHandler,Default_Handler
+
+    .weak   PVD_PVM_IRQHandler
+    .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+    .weak   TAMP_STAMP_IRQHandler
+    .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+    .weak   RTC_WKUP_IRQHandler
+    .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+    .weak   FLASH_IRQHandler
+    .thumb_set FLASH_IRQHandler,Default_Handler
+
+    .weak   RCC_IRQHandler
+    .thumb_set RCC_IRQHandler,Default_Handler
+
+    .weak   EXTI0_IRQHandler
+    .thumb_set EXTI0_IRQHandler,Default_Handler
+
+    .weak   EXTI1_IRQHandler
+    .thumb_set EXTI1_IRQHandler,Default_Handler
+
+    .weak   EXTI2_IRQHandler
+    .thumb_set EXTI2_IRQHandler,Default_Handler
+
+    .weak   EXTI3_IRQHandler
+    .thumb_set EXTI3_IRQHandler,Default_Handler
+
+    .weak   EXTI4_IRQHandler
+    .thumb_set EXTI4_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel1_IRQHandler
+    .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel2_IRQHandler
+    .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel3_IRQHandler
+    .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel4_IRQHandler
+    .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel5_IRQHandler
+    .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel6_IRQHandler
+    .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+    .weak   DMA1_Channel7_IRQHandler
+    .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+    .weak   ADC1_IRQHandler
+    .thumb_set ADC1_IRQHandler,Default_Handler
+
+    .weak   CAN1_TX_IRQHandler
+    .thumb_set CAN1_TX_IRQHandler,Default_Handler
+
+    .weak   CAN1_RX0_IRQHandler
+    .thumb_set CAN1_RX0_IRQHandler,Default_Handler
+
+    .weak   CAN1_RX1_IRQHandler
+    .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+    .weak   CAN1_SCE_IRQHandler
+    .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+    .weak   EXTI9_5_IRQHandler
+    .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+    .weak   TIM1_BRK_TIM15_IRQHandler
+    .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+    .weak   TIM1_UP_TIM16_IRQHandler
+    .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+    .weak   TIM1_TRG_COM_TIM17_IRQHandler
+    .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+    .weak   TIM1_CC_IRQHandler
+    .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+    .weak   TIM2_IRQHandler
+    .thumb_set TIM2_IRQHandler,Default_Handler
+
+    .weak   TIM3_IRQHandler
+    .thumb_set TIM3_IRQHandler,Default_Handler
+
+    .weak   TIM4_IRQHandler
+    .thumb_set TIM4_IRQHandler,Default_Handler
+
+    .weak   I2C1_EV_IRQHandler
+    .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+    .weak   I2C1_ER_IRQHandler
+    .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+    .weak   I2C2_EV_IRQHandler
+    .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+    .weak   I2C2_ER_IRQHandler
+    .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+    .weak   SPI1_IRQHandler
+    .thumb_set SPI1_IRQHandler,Default_Handler
+
+    .weak   SPI2_IRQHandler
+    .thumb_set SPI2_IRQHandler,Default_Handler
+
+    .weak   USART1_IRQHandler
+    .thumb_set USART1_IRQHandler,Default_Handler
+
+    .weak   USART2_IRQHandler
+    .thumb_set USART2_IRQHandler,Default_Handler
+
+    .weak   USART3_IRQHandler
+    .thumb_set USART3_IRQHandler,Default_Handler
+
+    .weak   EXTI15_10_IRQHandler
+    .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+    .weak   RTC_Alarm_IRQHandler
+    .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+    .weak   DFSDM1_FLT3_IRQHandler
+    .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+
+    .weak   TIM8_BRK_IRQHandler
+    .thumb_set TIM8_BRK_IRQHandler,Default_Handler
+
+    .weak   TIM8_UP_IRQHandler
+    .thumb_set TIM8_UP_IRQHandler,Default_Handler
+
+    .weak   TIM8_TRG_COM_IRQHandler
+    .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+
+    .weak   TIM8_CC_IRQHandler
+    .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+    .weak   FMC_IRQHandler
+    .thumb_set FMC_IRQHandler,Default_Handler
+
+    .weak   SDMMC1_IRQHandler
+    .thumb_set SDMMC1_IRQHandler,Default_Handler
+
+    .weak   TIM5_IRQHandler
+    .thumb_set TIM5_IRQHandler,Default_Handler
+
+    .weak   SPI3_IRQHandler
+    .thumb_set SPI3_IRQHandler,Default_Handler
+
+    .weak   UART4_IRQHandler
+    .thumb_set UART4_IRQHandler,Default_Handler
+
+    .weak   UART5_IRQHandler
+    .thumb_set UART5_IRQHandler,Default_Handler
+
+    .weak   TIM6_DAC_IRQHandler
+    .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+    .weak   TIM7_IRQHandler
+    .thumb_set TIM7_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel1_IRQHandler
+    .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel2_IRQHandler
+    .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel3_IRQHandler
+    .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel4_IRQHandler
+    .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel5_IRQHandler
+    .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+    .weak   DFSDM1_FLT0_IRQHandler
+    .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+
+    .weak   DFSDM1_FLT1_IRQHandler
+    .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+
+    .weak   DFSDM1_FLT2_IRQHandler
+    .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+
+    .weak   COMP_IRQHandler
+    .thumb_set COMP_IRQHandler,Default_Handler
+
+    .weak   LPTIM1_IRQHandler
+    .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+    .weak   LPTIM2_IRQHandler
+    .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+    .weak   OTG_FS_IRQHandler
+    .thumb_set OTG_FS_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel6_IRQHandler
+    .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+    .weak   DMA2_Channel7_IRQHandler
+    .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+    .weak   LPUART1_IRQHandler
+    .thumb_set LPUART1_IRQHandler,Default_Handler
+
+    .weak   OCTOSPI1_IRQHandler
+    .thumb_set OCTOSPI1_IRQHandler,Default_Handler
+
+    .weak   I2C3_EV_IRQHandler
+    .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+    .weak   I2C3_ER_IRQHandler
+    .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+    .weak   SAI1_IRQHandler
+    .thumb_set SAI1_IRQHandler,Default_Handler
+
+    .weak   SAI2_IRQHandler
+    .thumb_set SAI2_IRQHandler,Default_Handler
+
+    .weak   OCTOSPI2_IRQHandler
+    .thumb_set OCTOSPI2_IRQHandler,Default_Handler
+
+    .weak   TSC_IRQHandler
+    .thumb_set TSC_IRQHandler,Default_Handler
+
+    .weak   DSI_IRQHandler
+    .thumb_set DSI_IRQHandler,Default_Handler
+
+    .weak   AES_IRQHandler
+    .thumb_set AES_IRQHandler,Default_Handler
+
+    .weak   RNG_IRQHandler
+    .thumb_set RNG_IRQHandler,Default_Handler
+
+    .weak   FPU_IRQHandler
+    .thumb_set FPU_IRQHandler,Default_Handler
+
+    .weak   HASH_CRS_IRQHandler
+    .thumb_set HASH_CRS_IRQHandler,Default_Handler
+
+    .weak   I2C4_ER_IRQHandler
+    .thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+    .weak   I2C4_EV_IRQHandler
+    .thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+    .weak   DCMI_IRQHandler
+    .thumb_set DCMI_IRQHandler,Default_Handler
+
+    .weak   DMA2D_IRQHandler
+    .thumb_set DMA2D_IRQHandler,Default_Handler
+
+    .weak   LTDC_IRQHandler
+    .thumb_set LTDC_IRQHandler,Default_Handler
+
+    .weak   LTDC_ER_IRQHandler
+    .thumb_set LTDC_ER_IRQHandler,Default_Handler
+
+    .weak   GFXMMU_IRQHandler
+    .thumb_set GFXMMU_IRQHandler,Default_Handler
+
+    .weak   DMAMUX1_OVR_IRQHandler
+    .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

CMSIS/STM32L4xx/Source/Templates/iar/startup_stm32l412xx.s

@@ -0,0 +1,497 @@
+;********************************************************************************
+;* File Name          : startup_stm32l412xx.s
+;* Author             : MCD Application Team
+;* Description        : STM32L412xx Ultra Low Power Devices vector
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler             ; Reset Handler
+
+        DCD     NMI_Handler               ; NMI Handler
+        DCD     HardFault_Handler         ; Hard Fault Handler
+        DCD     MemManage_Handler         ; MPU Fault Handler
+        DCD     BusFault_Handler          ; Bus Fault Handler
+        DCD     UsageFault_Handler        ; Usage Fault Handler
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     SVC_Handler               ; SVCall Handler
+        DCD     DebugMon_Handler          ; Debug Monitor Handler
+        DCD     0                         ; Reserved
+        DCD     PendSV_Handler            ; PendSV Handler
+        DCD     SysTick_Handler           ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
+        DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+        DCD     FLASH_IRQHandler                  ; FLASH
+        DCD     RCC_IRQHandler                    ; RCC
+        DCD     EXTI0_IRQHandler                  ; EXTI Line0
+        DCD     EXTI1_IRQHandler                  ; EXTI Line1
+        DCD     EXTI2_IRQHandler                  ; EXTI Line2
+        DCD     EXTI3_IRQHandler                  ; EXTI Line3
+        DCD     EXTI4_IRQHandler                  ; EXTI Line4
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7
+        DCD     ADC1_2_IRQHandler                 ; ADC1, ADC2
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+        DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16
+        DCD     TIM1_TRG_COM_IRQHandler           ; TIM1 Trigger and Commutation
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+        DCD     TIM2_IRQHandler                   ; TIM2
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+        DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+        DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+        DCD     SPI1_IRQHandler                   ; SPI1
+        DCD     SPI2_IRQHandler                   ; SPI1
+        DCD     USART1_IRQHandler                 ; USART1
+        DCD     USART2_IRQHandler                 ; USART2
+        DCD     USART3_IRQHandler                 ; USART3
+        DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     TIM6_IRQHandler                   ; TIM6
+        DCD     0                                 ; Reserved
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     COMP_IRQHandler                   ; COMP Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LP TIM1 interrupt
+        DCD     LPTIM2_IRQHandler                 ; LP TIM2 interrupt
+        DCD     USB_IRQHandler                    ; USB FS
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7
+        DCD     LPUART1_IRQHandler                ; LP UART 1 interrupt
+        DCD     QUADSPI_IRQHandler                ; Quad SPI global interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 event
+        DCD     I2C3_ER_IRQHandler                ; I2C3 error
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; Touch Sense Controller global interrupt
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     RNG_IRQHandler                    ; RNG global interrupt
+        DCD     FPU_IRQHandler                    ; FPU interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_IRQHandler
+        B TAMP_STAMP_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_2_IRQHandler
+        B ADC1_2_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_TIM15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_TIM15_IRQHandler
+        B TIM1_BRK_TIM15_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+        B TIM1_TRG_COM_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+        B I2C2_EV_IRQHandler
+
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+        B I2C2_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+        B USART3_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK TIM6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_IRQHandler
+        B TIM6_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK USB_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_IRQHandler
+        B USB_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+       PUBWEAK TSC_IRQHandler
+       SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+       B TSC_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

CMSIS/STM32L4xx/Source/Templates/iar/startup_stm32l422xx.s

@@ -0,0 +1,502 @@
+;********************************************************************************
+;* File Name          : startup_stm32l422xx.s
+;* Author             : MCD Application Team
+;* Description        : STM32L422xx Ultra Low Power Devices vector
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler             ; Reset Handler
+
+        DCD     NMI_Handler               ; NMI Handler
+        DCD     HardFault_Handler         ; Hard Fault Handler
+        DCD     MemManage_Handler         ; MPU Fault Handler
+        DCD     BusFault_Handler          ; Bus Fault Handler
+        DCD     UsageFault_Handler        ; Usage Fault Handler
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     SVC_Handler               ; SVCall Handler
+        DCD     DebugMon_Handler          ; Debug Monitor Handler
+        DCD     0                         ; Reserved
+        DCD     PendSV_Handler            ; PendSV Handler
+        DCD     SysTick_Handler           ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
+        DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+        DCD     FLASH_IRQHandler                  ; FLASH
+        DCD     RCC_IRQHandler                    ; RCC
+        DCD     EXTI0_IRQHandler                  ; EXTI Line0
+        DCD     EXTI1_IRQHandler                  ; EXTI Line1
+        DCD     EXTI2_IRQHandler                  ; EXTI Line2
+        DCD     EXTI3_IRQHandler                  ; EXTI Line3
+        DCD     EXTI4_IRQHandler                  ; EXTI Line4
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7
+        DCD     ADC1_2_IRQHandler                 ; ADC1, ADC2
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+        DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16
+        DCD     TIM1_TRG_COM_IRQHandler           ; TIM1 Trigger and Commutation
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+        DCD     TIM2_IRQHandler                   ; TIM2
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+        DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+        DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+        DCD     SPI1_IRQHandler                   ; SPI1
+        DCD     SPI2_IRQHandler                   ; SPI1
+        DCD     USART1_IRQHandler                 ; USART1
+        DCD     USART2_IRQHandler                 ; USART2
+        DCD     USART3_IRQHandler                 ; USART3
+        DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     TIM6_IRQHandler                   ; TIM6
+        DCD     0                                 ; Reserved
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     COMP_IRQHandler                   ; COMP Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LP TIM1 interrupt
+        DCD     LPTIM2_IRQHandler                 ; LP TIM2 interrupt
+        DCD     USB_IRQHandler                    ; USB FS
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7
+        DCD     LPUART1_IRQHandler                ; LP UART 1 interrupt
+        DCD     QUADSPI_IRQHandler                ; Quad SPI global interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 event
+        DCD     I2C3_ER_IRQHandler                ; I2C3 error
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     TSC_IRQHandler                    ; Touch Sense Controller global interrupt
+        DCD     0                                 ; Reserved
+        DCD     AES_IRQHandler                    ; AES global interrupt
+        DCD     RNG_IRQHandler                    ; RNG global interrupt
+        DCD     FPU_IRQHandler                    ; FPU interrupt
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_IRQHandler
+        B TAMP_STAMP_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_2_IRQHandler
+        B ADC1_2_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_TIM15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_TIM15_IRQHandler
+        B TIM1_BRK_TIM15_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+        B TIM1_TRG_COM_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+        B I2C2_EV_IRQHandler
+
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+        B I2C2_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+        B USART3_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK TIM6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_IRQHandler
+        B TIM6_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK USB_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_IRQHandler
+        B USB_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+       PUBWEAK TSC_IRQHandler
+       SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+       B TSC_IRQHandler
+
+        PUBWEAK AES_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES_IRQHandler
+        B AES_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

CMSIS/STM32L4xx/Source/Templates/iar/startup_stm32l431xx.s

@@ -1,8 +1,6 @@
-;/********************* COPYRIGHT(c) 2017 STMicroelectronics ********************
+;********************************************************************************
 ;* File Name          : startup_stm32l431xx.s
 ;* Author             : MCD Application Team
-;* Version            : V1.3.2
-;* Date               : 16-June-2017
 ;* Description        : STM32L431xx Ultra Low Power Devices vector
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -15,27 +13,13 @@
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;********************************************************************************
 ;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
+;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.</center></h2>
 ;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
 ;*
 ;*******************************************************************************
 ;

CMSIS/STM32L4xx/Source/Templates/iar/startup_stm32l432xx.s

@@ -1,8 +1,6 @@
-;/********************* COPYRIGHT(c) 2017 STMicroelectronics ********************
+;********************************************************************************
 ;* File Name          : startup_stm32l432xx.s
 ;* Author             : MCD Application Team
-;* Version            : V1.3.2
-;* Date               : 16-June-2017
 ;* Description        : STM32L432xx Ultra Low Power Devices vector
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -15,27 +13,13 @@
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;********************************************************************************
 ;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
+;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.</center></h2>
 ;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
 ;*
 ;*******************************************************************************
 ;

CMSIS/STM32L4xx/Source/Templates/iar/startup_stm32l433xx.s

@@ -1,8 +1,6 @@
-;/********************* COPYRIGHT(c) 2017 STMicroelectronics ********************
+;********************************************************************************
 ;* File Name          : startup_stm32l433xx.s
 ;* Author             : MCD Application Team
-;* Version            : V1.3.2
-;* Date               : 16-June-2017
 ;* Description        : STM32L433xx Ultra Low Power Devices vector
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -15,27 +13,13 @@
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;********************************************************************************
 ;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
+;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.</center></h2>
 ;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
 ;*
 ;*******************************************************************************
 ;

CMSIS/STM32L4xx/Source/Templates/iar/startup_stm32l442xx.s

@@ -1,8 +1,6 @@
-;/********************* COPYRIGHT(c) 2017 STMicroelectronics ********************
+;********************************************************************************
 ;* File Name          : startup_stm32l442xx.s
 ;* Author             : MCD Application Team
-;* Version            : V1.3.2
-;* Date               : 16-June-2017
 ;* Description        : STM32L442xx Ultra Low Power Devices vector
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -15,27 +13,13 @@
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;********************************************************************************
 ;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
+;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.</center></h2>
 ;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
 ;*
 ;*******************************************************************************
 ;

CMSIS/STM32L4xx/Source/Templates/iar/startup_stm32l443xx.s

@@ -1,8 +1,6 @@
-;/********************* COPYRIGHT(c) 2017 STMicroelectronics ********************
+;********************************************************************************
 ;* File Name          : startup_stm32l443xx.s
 ;* Author             : MCD Application Team
-;* Version            : V1.3.2
-;* Date               : 16-June-2017
 ;* Description        : STM32L443xx Ultra Low Power Devices vector
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -15,27 +13,13 @@
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;********************************************************************************
 ;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
+;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.</center></h2>
 ;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
 ;*
 ;*******************************************************************************
 ;

CMSIS/STM32L4xx/Source/Templates/iar/startup_stm32l451xx.s

@@ -1,8 +1,6 @@
-;/********************* COPYRIGHT(c) 2017 STMicroelectronics ********************
+;********************************************************************************
 ;* File Name          : startup_stm32l451xx.s
 ;* Author             : MCD Application Team
-;* Version            : V1.3.2
-;* Date               : 16-June-2017
 ;* Description        : STM32L451xx Ultra Low Power Devices vector
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -15,27 +13,13 @@
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;********************************************************************************
 ;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
+;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.</center></h2>
 ;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
 ;*
 ;*******************************************************************************
 ;

CMSIS/STM32L4xx/Source/Templates/iar/startup_stm32l452xx.s

@@ -1,8 +1,6 @@
-;/********************* COPYRIGHT(c) 2017 STMicroelectronics ********************
+;********************************************************************************
 ;* File Name          : startup_stm32l452xx.s
 ;* Author             : MCD Application Team
-;* Version            : V1.3.2
-;* Date               : 16-June-2017
 ;* Description        : STM32L452xx Ultra Low Power Devices vector
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -15,27 +13,13 @@
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;********************************************************************************
 ;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
+;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.</center></h2>
 ;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
 ;*
 ;*******************************************************************************
 ;

CMSIS/STM32L4xx/Source/Templates/iar/startup_stm32l462xx.s

@@ -1,8 +1,6 @@
-;/********************* COPYRIGHT(c) 2017 STMicroelectronics ********************
+;********************************************************************************
 ;* File Name          : startup_stm32l462xx.s
 ;* Author             : MCD Application Team
-;* Version            : V1.3.2
-;* Date               : 16-June-2017
 ;* Description        : STM32L462xx Ultra Low Power Devices vector
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -15,27 +13,13 @@
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;********************************************************************************
 ;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
+;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.</center></h2>
 ;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
 ;*
 ;*******************************************************************************
 ;

CMSIS/STM32L4xx/Source/Templates/iar/startup_stm32l471xx.s

@@ -1,8 +1,6 @@
-;/********************* COPYRIGHT(c) 2017 STMicroelectronics ********************
+;********************************************************************************
 ;* File Name          : startup_stm32l471xx.s
 ;* Author             : MCD Application Team
-;* Version            : V1.3.2
-;* Date               : 16-June-2017
 ;* Description        : STM32L471xx Ultra Low Power Devices vector
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -15,27 +13,13 @@
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;********************************************************************************
 ;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
+;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.</center></h2>
 ;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
 ;*
 ;*******************************************************************************
 ;

CMSIS/STM32L4xx/Source/Templates/iar/startup_stm32l475xx.s

@@ -1,8 +1,6 @@
-;/********************* COPYRIGHT(c) 2017 STMicroelectronics ********************
+;********************************************************************************
 ;* File Name          : startup_stm32l475xx.s
 ;* Author             : MCD Application Team
-;* Version            : V1.3.2
-;* Date               : 16-June-2017
 ;* Description        : STM32L475xx Ultra Low Power Devices vector
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -15,27 +13,13 @@
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;********************************************************************************
 ;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
+;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.</center></h2>
 ;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
 ;*
 ;*******************************************************************************
 ;

CMSIS/STM32L4xx/Source/Templates/iar/startup_stm32l476xx.s

@@ -1,8 +1,6 @@
-;/********************* COPYRIGHT(c) 2017 STMicroelectronics ********************
+;********************************************************************************
 ;* File Name          : startup_stm32l476xx.s
 ;* Author             : MCD Application Team
-;* Version            : V1.3.2
-;* Date               : 16-June-2017
 ;* Description        : STM32L476xx Ultra Low Power Devices vector
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -15,27 +13,13 @@
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;********************************************************************************
 ;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
+;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.</center></h2>
 ;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
 ;*
 ;*******************************************************************************
 ;

CMSIS/STM32L4xx/Source/Templates/iar/startup_stm32l485xx.s

@@ -1,8 +1,6 @@
-;/********************* COPYRIGHT(c) 2017 STMicroelectronics ********************
+;********************************************************************************
 ;* File Name          : startup_stm32l485xx.s
 ;* Author             : MCD Application Team
-;* Version            : V1.3.2
-;* Date               : 16-June-2017
 ;* Description        : STM32L485xx Ultra Low Power Devices vector
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -15,27 +13,13 @@
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;********************************************************************************
 ;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
+;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.</center></h2>
 ;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
 ;*
 ;*******************************************************************************
 ;

CMSIS/STM32L4xx/Source/Templates/iar/startup_stm32l486xx.s

@@ -1,8 +1,6 @@
-;/********************* COPYRIGHT(c) 2017 STMicroelectronics ********************
+;********************************************************************************
 ;* File Name          : startup_stm32l486xx.s
 ;* Author             : MCD Application Team
-;* Version            : V1.3.2
-;* Date               : 16-June-2017
 ;* Description        : STM32L486xx Ultra Low Power Devices vector
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -15,27 +13,13 @@
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;********************************************************************************
 ;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
+;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.</center></h2>
 ;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
 ;*
 ;*******************************************************************************
 ;

CMSIS/STM32L4xx/Source/Templates/iar/startup_stm32l496xx.s

@@ -1,8 +1,6 @@
-;/********************* COPYRIGHT(c) 2017 STMicroelectronics ********************
+;********************************************************************************
 ;* File Name          : startup_stm32l496xx.s
 ;* Author             : MCD Application Team
-;* Version            : V1.3.2
-;* Date               : 16-June-2017
 ;* Description        : STM32L496xx Ultra Low Power Devices vector
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -15,27 +13,13 @@
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;********************************************************************************
 ;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
+;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.</center></h2>
 ;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
 ;*
 ;*******************************************************************************
 ;

CMSIS/STM32L4xx/Source/Templates/iar/startup_stm32l4a6xx.s

@@ -1,8 +1,6 @@
-;/********************* COPYRIGHT(c) 2017 STMicroelectronics ********************
+;********************************************************************************
 ;* File Name          : startup_stm32l4a6xx.s
 ;* Author             : MCD Application Team
-;* Version            : V1.3.2
-;* Date               : 16-June-2017
 ;* Description        : STM32L4A6xx Ultra Low Power Devices vector
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -15,27 +13,13 @@
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;********************************************************************************
 ;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
+;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.</center></h2>
 ;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
 ;*
 ;*******************************************************************************
 ;

CMSIS/STM32L4xx/Source/Templates/iar/startup_stm32l4p5xx.s

@@ -0,0 +1,659 @@
+;********************************************************************************
+;* File Name          : startup_stm32l4p5xx.s
+;* Author             : MCD Application Team
+;* Description        : STM32L4P5xx Ultra Low Power Devices vector
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler             ; Reset Handler
+
+        DCD     NMI_Handler               ; NMI Handler
+        DCD     HardFault_Handler         ; Hard Fault Handler
+        DCD     MemManage_Handler         ; MPU Fault Handler
+        DCD     BusFault_Handler          ; Bus Fault Handler
+        DCD     UsageFault_Handler        ; Usage Fault Handler
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     SVC_Handler               ; SVCall Handler
+        DCD     DebugMon_Handler          ; Debug Monitor Handler
+        DCD     0                         ; Reserved
+        DCD     PendSV_Handler            ; PendSV Handler
+        DCD     SysTick_Handler           ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
+        DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+        DCD     FLASH_IRQHandler                  ; FLASH
+        DCD     RCC_IRQHandler                    ; RCC
+        DCD     EXTI0_IRQHandler                  ; EXTI Line0
+        DCD     EXTI1_IRQHandler                  ; EXTI Line1
+        DCD     EXTI2_IRQHandler                  ; EXTI Line2
+        DCD     EXTI3_IRQHandler                  ; EXTI Line3
+        DCD     EXTI4_IRQHandler                  ; EXTI Line4
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7
+        DCD     ADC1_2_IRQHandler                 ; ADC1, ADC2
+        DCD     CAN1_TX_IRQHandler                ; CAN1 TX
+        DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0
+        DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1
+        DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE
+        DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+        DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Commutation and TIM17
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+        DCD     TIM2_IRQHandler                   ; TIM2
+        DCD     TIM3_IRQHandler                   ; TIM3
+        DCD     TIM4_IRQHandler                   ; TIM4
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+        DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+        DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+        DCD     SPI1_IRQHandler                   ; SPI1
+        DCD     SPI2_IRQHandler                   ; SPI2
+        DCD     USART1_IRQHandler                 ; USART1
+        DCD     USART2_IRQHandler                 ; USART2
+        DCD     USART3_IRQHandler                 ; USART3
+        DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) and RTC SSR Underflow through EXTI Line
+        DCD     0                                 ; Reserved
+        DCD     TIM8_BRK_IRQHandler               ; TIM8 Break Interrupt
+        DCD     TIM8_UP_IRQHandler                ; TIM8 Update Interrupt
+        DCD     TIM8_TRG_COM_IRQHandler           ; TIM8 Trigger and Commutation Interrupt
+        DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt
+        DCD     SDMMC2_IRQHandler                 ; SDMMC2
+        DCD     FMC_IRQHandler                    ; FMC
+        DCD     SDMMC1_IRQHandler                 ; SDMMC1
+        DCD     TIM5_IRQHandler                   ; TIM5
+        DCD     SPI3_IRQHandler                   ; SPI3
+        DCD     UART4_IRQHandler                  ; UART4
+        DCD     UART5_IRQHandler                  ; UART5
+        DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+        DCD     TIM7_IRQHandler                   ; TIM7
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5
+        DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM1 Filter 0 global Interrupt
+        DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM1 Filter 1 global Interrupt
+        DCD     0                                 ; Reserved
+        DCD     COMP_IRQHandler                   ; COMP Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LP TIM1 interrupt
+        DCD     LPTIM2_IRQHandler                 ; LP TIM2 interrupt
+        DCD     OTG_FS_IRQHandler                 ; USB OTG FS
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7
+        DCD     LPUART1_IRQHandler                ; LP UART 1 interrupt
+        DCD     OCTOSPI1_IRQHandler               ; OctoSPI1 global interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 event
+        DCD     I2C3_ER_IRQHandler                ; I2C3 error
+        DCD     SAI1_IRQHandler                   ; Serial Audio Interface 1 global interrupt
+        DCD     SAI2_IRQHandler                   ; Serial Audio Interface 2 global interrupt
+        DCD     OCTOSPI2_IRQHandler               ; OctoSPI2 global interrupt
+        DCD     TSC_IRQHandler                    ; Touch Sense Controller global interrupt
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     RNG_IRQHandler                    ; RNG global interrupt
+        DCD     FPU_IRQHandler                    ; FPU
+        DCD     HASH_CRS_IRQHandler               ; HASH and CRS global interrupt
+        DCD     I2C4_ER_IRQHandler                ; I2C4 error
+        DCD     I2C4_EV_IRQHandler                ; I2C4 event
+        DCD     DCMI_PSSI_IRQHandler              ; DCMI and PSSI global interrupt
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     DMA2D_IRQHandler                  ; DMA2D global interrupt
+        DCD     LTDC_IRQHandler                   ; LTDC global interrupt
+        DCD     LTDC_ER_IRQHandler                ; LTDC error global interrupt
+        DCD     0                                 ; Reserved
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX1 overrun global interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_IRQHandler
+        B TAMP_STAMP_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_2_IRQHandler
+        B ADC1_2_IRQHandler
+
+        PUBWEAK CAN1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_TX_IRQHandler
+        B CAN1_TX_IRQHandler
+
+        PUBWEAK CAN1_RX0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_RX0_IRQHandler
+        B CAN1_RX0_IRQHandler
+
+        PUBWEAK CAN1_RX1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_RX1_IRQHandler
+        B CAN1_RX1_IRQHandler
+
+        PUBWEAK CAN1_SCE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_SCE_IRQHandler
+        B CAN1_SCE_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_TIM15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_TIM15_IRQHandler
+        B TIM1_BRK_TIM15_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+        B TIM3_IRQHandler
+
+        PUBWEAK TIM4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+        B TIM4_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+        B I2C2_EV_IRQHandler
+
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+        B I2C2_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+        B USART3_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK TIM8_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_IRQHandler
+        B TIM8_BRK_IRQHandler
+
+        PUBWEAK TIM8_UP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_IRQHandler
+        B TIM8_UP_IRQHandler
+
+        PUBWEAK TIM8_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_IRQHandler
+        B TIM8_TRG_COM_IRQHandler
+
+        PUBWEAK TIM8_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+        B TIM8_CC_IRQHandler
+
+        PUBWEAK SDMMC2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC2_IRQHandler
+        B SDMMC2_IRQHandler
+
+        PUBWEAK FMC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+        B FMC_IRQHandler
+
+        PUBWEAK SDMMC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+        B SDMMC1_IRQHandler
+
+        PUBWEAK TIM5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+        B TIM5_IRQHandler
+
+        PUBWEAK SPI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+        B SPI3_IRQHandler
+
+        PUBWEAK UART4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+        B UART4_IRQHandler
+
+        PUBWEAK UART5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+        B UART5_IRQHandler
+
+        PUBWEAK TIM6_DAC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+        B TIM6_DAC_IRQHandler
+
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+        B TIM7_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DFSDM1_FLT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT0_IRQHandler
+        B DFSDM1_FLT0_IRQHandler
+
+        PUBWEAK DFSDM1_FLT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT1_IRQHandler
+        B DFSDM1_FLT1_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK OTG_FS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_IRQHandler
+        B OTG_FS_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK OCTOSPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI1_IRQHandler
+        B OCTOSPI1_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SAI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+        B SAI1_IRQHandler
+
+       PUBWEAK SAI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SAI2_IRQHandler
+        B SAI2_IRQHandler
+
+        PUBWEAK OCTOSPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI2_IRQHandler
+        B OCTOSPI2_IRQHandler
+
+       PUBWEAK TSC_IRQHandler
+       SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+       B TSC_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK HASH_CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HASH_CRS_IRQHandler
+        B HASH_CRS_IRQHandler
+
+        PUBWEAK I2C4_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_ER_IRQHandler
+        B I2C4_ER_IRQHandler
+
+        PUBWEAK I2C4_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_EV_IRQHandler
+        B I2C4_EV_IRQHandler
+
+        PUBWEAK DMA2D_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2D_IRQHandler
+        B DMA2D_IRQHandler
+
+        PUBWEAK DCMI_PSSI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DCMI_PSSI_IRQHandler
+        B DCMI_PSSI_IRQHandler
+
+        PUBWEAK LTDC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_IRQHandler
+        B LTDC_IRQHandler
+
+        PUBWEAK LTDC_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_ER_IRQHandler
+        B LTDC_ER_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

CMSIS/STM32L4xx/Source/Templates/iar/startup_stm32l4q5xx.s

@@ -0,0 +1,669 @@
+;********************************************************************************
+;* File Name          : startup_stm32l4q5xx.s
+;* Author             : MCD Application Team
+;* Description        : STM32L4Q5xx Ultra Low Power Devices vector
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler             ; Reset Handler
+
+        DCD     NMI_Handler               ; NMI Handler
+        DCD     HardFault_Handler         ; Hard Fault Handler
+        DCD     MemManage_Handler         ; MPU Fault Handler
+        DCD     BusFault_Handler          ; Bus Fault Handler
+        DCD     UsageFault_Handler        ; Usage Fault Handler
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     SVC_Handler               ; SVCall Handler
+        DCD     DebugMon_Handler          ; Debug Monitor Handler
+        DCD     0                         ; Reserved
+        DCD     PendSV_Handler            ; PendSV Handler
+        DCD     SysTick_Handler           ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
+        DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+        DCD     FLASH_IRQHandler                  ; FLASH
+        DCD     RCC_IRQHandler                    ; RCC
+        DCD     EXTI0_IRQHandler                  ; EXTI Line0
+        DCD     EXTI1_IRQHandler                  ; EXTI Line1
+        DCD     EXTI2_IRQHandler                  ; EXTI Line2
+        DCD     EXTI3_IRQHandler                  ; EXTI Line3
+        DCD     EXTI4_IRQHandler                  ; EXTI Line4
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7
+        DCD     ADC1_2_IRQHandler                 ; ADC1, ADC2
+        DCD     CAN1_TX_IRQHandler                ; CAN1 TX
+        DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0
+        DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1
+        DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE
+        DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+        DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Commutation and TIM17
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+        DCD     TIM2_IRQHandler                   ; TIM2
+        DCD     TIM3_IRQHandler                   ; TIM3
+        DCD     TIM4_IRQHandler                   ; TIM4
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+        DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+        DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+        DCD     SPI1_IRQHandler                   ; SPI1
+        DCD     SPI2_IRQHandler                   ; SPI2
+        DCD     USART1_IRQHandler                 ; USART1
+        DCD     USART2_IRQHandler                 ; USART2
+        DCD     USART3_IRQHandler                 ; USART3
+        DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) and RTC SSR Underflow through EXTI Line
+        DCD     0                                 ; Reserved
+        DCD     TIM8_BRK_IRQHandler               ; TIM8 Break Interrupt
+        DCD     TIM8_UP_IRQHandler                ; TIM8 Update Interrupt
+        DCD     TIM8_TRG_COM_IRQHandler           ; TIM8 Trigger and Commutation Interrupt
+        DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt
+        DCD     SDMMC2_IRQHandler                 ; SDMMC2
+        DCD     FMC_IRQHandler                    ; FMC
+        DCD     SDMMC1_IRQHandler                 ; SDMMC1
+        DCD     TIM5_IRQHandler                   ; TIM5
+        DCD     SPI3_IRQHandler                   ; SPI3
+        DCD     UART4_IRQHandler                  ; UART4
+        DCD     UART5_IRQHandler                  ; UART5
+        DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+        DCD     TIM7_IRQHandler                   ; TIM7
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5
+        DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM1 Filter 0 global Interrupt
+        DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM1 Filter 1 global Interrupt
+        DCD     0                                 ; Reserved
+        DCD     COMP_IRQHandler                   ; COMP Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LP TIM1 interrupt
+        DCD     LPTIM2_IRQHandler                 ; LP TIM2 interrupt
+        DCD     OTG_FS_IRQHandler                 ; USB OTG FS
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7
+        DCD     LPUART1_IRQHandler                ; LP UART 1 interrupt
+        DCD     OCTOSPI1_IRQHandler               ; OctoSPI1 global interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 event
+        DCD     I2C3_ER_IRQHandler                ; I2C3 error
+        DCD     SAI1_IRQHandler                   ; Serial Audio Interface 1 global interrupt
+        DCD     SAI2_IRQHandler                   ; Serial Audio Interface 2 global interrupt
+        DCD     OCTOSPI2_IRQHandler               ; OctoSPI2 global interrupt
+        DCD     TSC_IRQHandler                    ; Touch Sense Controller global interrupt
+        DCD     0                                 ; Reserved
+        DCD     AES_IRQHandler                    ; AES global interrupt
+        DCD     RNG_IRQHandler                    ; RNG global interrupt
+        DCD     FPU_IRQHandler                    ; FPU
+        DCD     HASH_CRS_IRQHandler               ; HASH and CRS interrupt
+        DCD     I2C4_ER_IRQHandler                ; I2C4 error
+        DCD     I2C4_EV_IRQHandler                ; I2C4 event
+        DCD     DCMI_PSSI_IRQHandler              ; DCMI, PSSI global interrupt
+        DCD     PKA_IRQHandler                    ; PKA global interrupt
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     DMA2D_IRQHandler                  ; DMA2D global interrupt
+        DCD     LTDC_IRQHandler                   ; LTDC global interrupt
+        DCD     LTDC_ER_IRQHandler                ; LTDC error global interrupt
+        DCD     0                                 ; Reserved
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX1 overrun global interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_IRQHandler
+        B TAMP_STAMP_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_2_IRQHandler
+        B ADC1_2_IRQHandler
+
+        PUBWEAK CAN1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_TX_IRQHandler
+        B CAN1_TX_IRQHandler
+
+        PUBWEAK CAN1_RX0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_RX0_IRQHandler
+        B CAN1_RX0_IRQHandler
+
+        PUBWEAK CAN1_RX1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_RX1_IRQHandler
+        B CAN1_RX1_IRQHandler
+
+        PUBWEAK CAN1_SCE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_SCE_IRQHandler
+        B CAN1_SCE_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_TIM15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_TIM15_IRQHandler
+        B TIM1_BRK_TIM15_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+        B TIM3_IRQHandler
+
+        PUBWEAK TIM4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+        B TIM4_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+        B I2C2_EV_IRQHandler
+
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+        B I2C2_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+        B USART3_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK TIM8_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_IRQHandler
+        B TIM8_BRK_IRQHandler
+
+        PUBWEAK TIM8_UP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_IRQHandler
+        B TIM8_UP_IRQHandler
+
+        PUBWEAK TIM8_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_IRQHandler
+        B TIM8_TRG_COM_IRQHandler
+
+        PUBWEAK TIM8_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+        B TIM8_CC_IRQHandler
+
+        PUBWEAK SDMMC2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC2_IRQHandler
+        B SDMMC2_IRQHandler
+
+        PUBWEAK FMC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+        B FMC_IRQHandler
+
+        PUBWEAK SDMMC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+        B SDMMC1_IRQHandler
+
+        PUBWEAK TIM5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+        B TIM5_IRQHandler
+
+        PUBWEAK SPI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+        B SPI3_IRQHandler
+
+        PUBWEAK UART4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+        B UART4_IRQHandler
+
+        PUBWEAK UART5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+        B UART5_IRQHandler
+
+        PUBWEAK TIM6_DAC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+        B TIM6_DAC_IRQHandler
+
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+        B TIM7_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DFSDM1_FLT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT0_IRQHandler
+        B DFSDM1_FLT0_IRQHandler
+
+        PUBWEAK DFSDM1_FLT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT1_IRQHandler
+        B DFSDM1_FLT1_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK OTG_FS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_IRQHandler
+        B OTG_FS_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK OCTOSPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI1_IRQHandler
+        B OCTOSPI1_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SAI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+        B SAI1_IRQHandler
+
+       PUBWEAK SAI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SAI2_IRQHandler
+        B SAI2_IRQHandler
+
+        PUBWEAK OCTOSPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI2_IRQHandler
+        B OCTOSPI2_IRQHandler
+
+       PUBWEAK TSC_IRQHandler
+       SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+       B TSC_IRQHandler
+
+        PUBWEAK AES_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES_IRQHandler
+        B AES_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK HASH_CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HASH_CRS_IRQHandler
+        B HASH_CRS_IRQHandler
+
+        PUBWEAK I2C4_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_ER_IRQHandler
+        B I2C4_ER_IRQHandler
+
+        PUBWEAK I2C4_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_EV_IRQHandler
+        B I2C4_EV_IRQHandler
+
+        PUBWEAK DMA2D_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2D_IRQHandler
+        B DMA2D_IRQHandler
+
+        PUBWEAK DCMI_PSSI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DCMI_PSSI_IRQHandler
+        B DCMI_PSSI_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK LTDC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_IRQHandler
+        B LTDC_IRQHandler
+
+        PUBWEAK LTDC_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_ER_IRQHandler
+        B LTDC_ER_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

CMSIS/STM32L4xx/Source/Templates/iar/startup_stm32l4r5xx.s

@@ -0,0 +1,669 @@
+;********************************************************************************
+;* File Name          : startup_stm32l4r5xx.s
+;* Author             : MCD Application Team
+;* Description        : STM32L4R5xx Ultra Low Power Devices vector
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler             ; Reset Handler
+
+        DCD     NMI_Handler               ; NMI Handler
+        DCD     HardFault_Handler         ; Hard Fault Handler
+        DCD     MemManage_Handler         ; MPU Fault Handler
+        DCD     BusFault_Handler          ; Bus Fault Handler
+        DCD     UsageFault_Handler        ; Usage Fault Handler
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     SVC_Handler               ; SVCall Handler
+        DCD     DebugMon_Handler          ; Debug Monitor Handler
+        DCD     0                         ; Reserved
+        DCD     PendSV_Handler            ; PendSV Handler
+        DCD     SysTick_Handler           ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
+        DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+        DCD     FLASH_IRQHandler                  ; FLASH
+        DCD     RCC_IRQHandler                    ; RCC
+        DCD     EXTI0_IRQHandler                  ; EXTI Line0
+        DCD     EXTI1_IRQHandler                  ; EXTI Line1
+        DCD     EXTI2_IRQHandler                  ; EXTI Line2
+        DCD     EXTI3_IRQHandler                  ; EXTI Line3
+        DCD     EXTI4_IRQHandler                  ; EXTI Line4
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7
+        DCD     ADC1_IRQHandler                   ; ADC1
+        DCD     CAN1_TX_IRQHandler                ; CAN1 TX
+        DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0
+        DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1
+        DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE
+        DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+        DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Commutation and TIM17
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+        DCD     TIM2_IRQHandler                   ; TIM2
+        DCD     TIM3_IRQHandler                   ; TIM3
+        DCD     TIM4_IRQHandler                   ; TIM4
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+        DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+        DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+        DCD     SPI1_IRQHandler                   ; SPI1
+        DCD     SPI2_IRQHandler                   ; SPI2
+        DCD     USART1_IRQHandler                 ; USART1
+        DCD     USART2_IRQHandler                 ; USART2
+        DCD     USART3_IRQHandler                 ; USART3
+        DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+        DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM1 Filter 3 global Interrupt
+        DCD     TIM8_BRK_IRQHandler               ; TIM8 Break Interrupt
+        DCD     TIM8_UP_IRQHandler                ; TIM8 Update Interrupt
+        DCD     TIM8_TRG_COM_IRQHandler           ; TIM8 Trigger and Commutation Interrupt
+        DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt
+        DCD     0                                 ; Reserved
+        DCD     FMC_IRQHandler                    ; FMC
+        DCD     SDMMC1_IRQHandler                 ; SDMMC1
+        DCD     TIM5_IRQHandler                   ; TIM5
+        DCD     SPI3_IRQHandler                   ; SPI3
+        DCD     UART4_IRQHandler                  ; UART4
+        DCD     UART5_IRQHandler                  ; UART5
+        DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+        DCD     TIM7_IRQHandler                   ; TIM7
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5
+        DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM1 Filter 0 global Interrupt
+        DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM1 Filter 1 global Interrupt
+        DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM1 Filter 2 global Interrupt
+        DCD     COMP_IRQHandler                   ; COMP Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LP TIM1 interrupt
+        DCD     LPTIM2_IRQHandler                 ; LP TIM2 interrupt
+        DCD     OTG_FS_IRQHandler                 ; USB OTG FS
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7
+        DCD     LPUART1_IRQHandler                ; LP UART 1 interrupt
+        DCD     OCTOSPI1_IRQHandler               ; OctoSPI1 global interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 event
+        DCD     I2C3_ER_IRQHandler                ; I2C3 error
+        DCD     SAI1_IRQHandler                   ; Serial Audio Interface 1 global interrupt
+        DCD     SAI2_IRQHandler                   ; Serial Audio Interface 2 global interrupt
+        DCD     OCTOSPI2_IRQHandler               ; OctoSPI2 global interrupt
+        DCD     TSC_IRQHandler                    ; Touch Sense Controller global interrupt
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     RNG_IRQHandler                    ; RNG global interrupt
+        DCD     FPU_IRQHandler                    ; FPU
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     I2C4_ER_IRQHandler                ; I2C4 error
+        DCD     I2C4_EV_IRQHandler                ; I2C4 event
+        DCD     DCMI_IRQHandler                   ; DCMI global interrupt
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     DMA2D_IRQHandler                  ; DMA2D global interrupt
+        DCD     LTDC_IRQHandler                   ; LTDC global interrupt
+        DCD     LTDC_ER_IRQHandler                ; LTDC error global interrupt
+        DCD     GFXMMU_IRQHandler                 ; GFXMMU global interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX1 overrun global interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_IRQHandler
+        B TAMP_STAMP_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK CAN1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_TX_IRQHandler
+        B CAN1_TX_IRQHandler
+
+        PUBWEAK CAN1_RX0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_RX0_IRQHandler
+        B CAN1_RX0_IRQHandler
+
+        PUBWEAK CAN1_RX1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_RX1_IRQHandler
+        B CAN1_RX1_IRQHandler
+
+        PUBWEAK CAN1_SCE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_SCE_IRQHandler
+        B CAN1_SCE_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_TIM15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_TIM15_IRQHandler
+        B TIM1_BRK_TIM15_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+        B TIM3_IRQHandler
+
+        PUBWEAK TIM4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+        B TIM4_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+        B I2C2_EV_IRQHandler
+
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+        B I2C2_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+        B USART3_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK DFSDM1_FLT3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT3_IRQHandler
+        B DFSDM1_FLT3_IRQHandler
+
+        PUBWEAK TIM8_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_IRQHandler
+        B TIM8_BRK_IRQHandler
+
+        PUBWEAK TIM8_UP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_IRQHandler
+        B TIM8_UP_IRQHandler
+
+        PUBWEAK TIM8_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_IRQHandler
+        B TIM8_TRG_COM_IRQHandler
+
+        PUBWEAK TIM8_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+        B TIM8_CC_IRQHandler
+
+        PUBWEAK FMC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+        B FMC_IRQHandler
+
+        PUBWEAK SDMMC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+        B SDMMC1_IRQHandler
+
+        PUBWEAK TIM5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+        B TIM5_IRQHandler
+
+        PUBWEAK SPI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+        B SPI3_IRQHandler
+
+        PUBWEAK UART4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+        B UART4_IRQHandler
+
+        PUBWEAK UART5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+        B UART5_IRQHandler
+
+        PUBWEAK TIM6_DAC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+        B TIM6_DAC_IRQHandler
+
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+        B TIM7_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DFSDM1_FLT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT0_IRQHandler
+        B DFSDM1_FLT0_IRQHandler
+
+        PUBWEAK DFSDM1_FLT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT1_IRQHandler
+        B DFSDM1_FLT1_IRQHandler
+
+        PUBWEAK DFSDM1_FLT2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT2_IRQHandler
+        B DFSDM1_FLT2_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK OTG_FS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_IRQHandler
+        B OTG_FS_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK OCTOSPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI1_IRQHandler
+        B OCTOSPI1_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SAI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+        B SAI1_IRQHandler
+
+       PUBWEAK SAI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SAI2_IRQHandler
+        B SAI2_IRQHandler
+
+        PUBWEAK OCTOSPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI2_IRQHandler
+        B OCTOSPI2_IRQHandler
+
+       PUBWEAK TSC_IRQHandler
+       SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+       B TSC_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK I2C4_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_ER_IRQHandler
+        B I2C4_ER_IRQHandler
+
+        PUBWEAK I2C4_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_EV_IRQHandler
+        B I2C4_EV_IRQHandler
+
+        PUBWEAK DMA2D_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2D_IRQHandler
+        B DMA2D_IRQHandler
+
+        PUBWEAK DCMI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DCMI_IRQHandler
+        B DCMI_IRQHandler
+
+        PUBWEAK LTDC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_IRQHandler
+        B LTDC_IRQHandler
+
+        PUBWEAK LTDC_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_ER_IRQHandler
+        B LTDC_ER_IRQHandler
+
+        PUBWEAK GFXMMU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GFXMMU_IRQHandler
+        B GFXMMU_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

CMSIS/STM32L4xx/Source/Templates/iar/startup_stm32l4r7xx.s

@@ -0,0 +1,669 @@
+;********************************************************************************
+;* File Name          : startup_stm32l4r7xx.s
+;* Author             : MCD Application Team
+;* Description        : STM32L4R7xx Ultra Low Power Devices vector
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler             ; Reset Handler
+
+        DCD     NMI_Handler               ; NMI Handler
+        DCD     HardFault_Handler         ; Hard Fault Handler
+        DCD     MemManage_Handler         ; MPU Fault Handler
+        DCD     BusFault_Handler          ; Bus Fault Handler
+        DCD     UsageFault_Handler        ; Usage Fault Handler
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     SVC_Handler               ; SVCall Handler
+        DCD     DebugMon_Handler          ; Debug Monitor Handler
+        DCD     0                         ; Reserved
+        DCD     PendSV_Handler            ; PendSV Handler
+        DCD     SysTick_Handler           ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
+        DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+        DCD     FLASH_IRQHandler                  ; FLASH
+        DCD     RCC_IRQHandler                    ; RCC
+        DCD     EXTI0_IRQHandler                  ; EXTI Line0
+        DCD     EXTI1_IRQHandler                  ; EXTI Line1
+        DCD     EXTI2_IRQHandler                  ; EXTI Line2
+        DCD     EXTI3_IRQHandler                  ; EXTI Line3
+        DCD     EXTI4_IRQHandler                  ; EXTI Line4
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7
+        DCD     ADC1_IRQHandler                   ; ADC1
+        DCD     CAN1_TX_IRQHandler                ; CAN1 TX
+        DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0
+        DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1
+        DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE
+        DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+        DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Commutation and TIM17
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+        DCD     TIM2_IRQHandler                   ; TIM2
+        DCD     TIM3_IRQHandler                   ; TIM3
+        DCD     TIM4_IRQHandler                   ; TIM4
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+        DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+        DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+        DCD     SPI1_IRQHandler                   ; SPI1
+        DCD     SPI2_IRQHandler                   ; SPI2
+        DCD     USART1_IRQHandler                 ; USART1
+        DCD     USART2_IRQHandler                 ; USART2
+        DCD     USART3_IRQHandler                 ; USART3
+        DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+        DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM1 Filter 3 global Interrupt
+        DCD     TIM8_BRK_IRQHandler               ; TIM8 Break Interrupt
+        DCD     TIM8_UP_IRQHandler                ; TIM8 Update Interrupt
+        DCD     TIM8_TRG_COM_IRQHandler           ; TIM8 Trigger and Commutation Interrupt
+        DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt
+        DCD     0                                 ; Reserved
+        DCD     FMC_IRQHandler                    ; FMC
+        DCD     SDMMC1_IRQHandler                 ; SDMMC1
+        DCD     TIM5_IRQHandler                   ; TIM5
+        DCD     SPI3_IRQHandler                   ; SPI3
+        DCD     UART4_IRQHandler                  ; UART4
+        DCD     UART5_IRQHandler                  ; UART5
+        DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+        DCD     TIM7_IRQHandler                   ; TIM7
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5
+        DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM1 Filter 0 global Interrupt
+        DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM1 Filter 1 global Interrupt
+        DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM1 Filter 2 global Interrupt
+        DCD     COMP_IRQHandler                   ; COMP Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LP TIM1 interrupt
+        DCD     LPTIM2_IRQHandler                 ; LP TIM2 interrupt
+        DCD     OTG_FS_IRQHandler                 ; USB OTG FS
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7
+        DCD     LPUART1_IRQHandler                ; LP UART 1 interrupt
+        DCD     OCTOSPI1_IRQHandler               ; OctoSPI1 global interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 event
+        DCD     I2C3_ER_IRQHandler                ; I2C3 error
+        DCD     SAI1_IRQHandler                   ; Serial Audio Interface 1 global interrupt
+        DCD     SAI2_IRQHandler                   ; Serial Audio Interface 2 global interrupt
+        DCD     OCTOSPI2_IRQHandler               ; OctoSPI2 global interrupt
+        DCD     TSC_IRQHandler                    ; Touch Sense Controller global interrupt
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     RNG_IRQHandler                    ; RNG global interrupt
+        DCD     FPU_IRQHandler                    ; FPU
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     I2C4_ER_IRQHandler                ; I2C4 error
+        DCD     I2C4_EV_IRQHandler                ; I2C4 event
+        DCD     DCMI_IRQHandler                   ; DCMI global interrupt
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     DMA2D_IRQHandler                  ; DMA2D global interrupt
+        DCD     LTDC_IRQHandler                   ; LTDC global interrupt
+        DCD     LTDC_ER_IRQHandler                ; LTDC error global interrupt
+        DCD     GFXMMU_IRQHandler                 ; GFXMMU global interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX1 overrun global interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_IRQHandler
+        B TAMP_STAMP_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK CAN1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_TX_IRQHandler
+        B CAN1_TX_IRQHandler
+
+        PUBWEAK CAN1_RX0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_RX0_IRQHandler
+        B CAN1_RX0_IRQHandler
+
+        PUBWEAK CAN1_RX1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_RX1_IRQHandler
+        B CAN1_RX1_IRQHandler
+
+        PUBWEAK CAN1_SCE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_SCE_IRQHandler
+        B CAN1_SCE_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_TIM15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_TIM15_IRQHandler
+        B TIM1_BRK_TIM15_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+        B TIM3_IRQHandler
+
+        PUBWEAK TIM4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+        B TIM4_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+        B I2C2_EV_IRQHandler
+
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+        B I2C2_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+        B USART3_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK DFSDM1_FLT3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT3_IRQHandler
+        B DFSDM1_FLT3_IRQHandler
+
+        PUBWEAK TIM8_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_IRQHandler
+        B TIM8_BRK_IRQHandler
+
+        PUBWEAK TIM8_UP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_IRQHandler
+        B TIM8_UP_IRQHandler
+
+        PUBWEAK TIM8_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_IRQHandler
+        B TIM8_TRG_COM_IRQHandler
+
+        PUBWEAK TIM8_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+        B TIM8_CC_IRQHandler
+
+        PUBWEAK FMC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+        B FMC_IRQHandler
+
+        PUBWEAK SDMMC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+        B SDMMC1_IRQHandler
+
+        PUBWEAK TIM5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+        B TIM5_IRQHandler
+
+        PUBWEAK SPI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+        B SPI3_IRQHandler
+
+        PUBWEAK UART4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+        B UART4_IRQHandler
+
+        PUBWEAK UART5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+        B UART5_IRQHandler
+
+        PUBWEAK TIM6_DAC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+        B TIM6_DAC_IRQHandler
+
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+        B TIM7_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DFSDM1_FLT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT0_IRQHandler
+        B DFSDM1_FLT0_IRQHandler
+
+        PUBWEAK DFSDM1_FLT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT1_IRQHandler
+        B DFSDM1_FLT1_IRQHandler
+
+        PUBWEAK DFSDM1_FLT2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT2_IRQHandler
+        B DFSDM1_FLT2_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK OTG_FS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_IRQHandler
+        B OTG_FS_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK OCTOSPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI1_IRQHandler
+        B OCTOSPI1_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SAI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+        B SAI1_IRQHandler
+
+       PUBWEAK SAI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SAI2_IRQHandler
+        B SAI2_IRQHandler
+
+        PUBWEAK OCTOSPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI2_IRQHandler
+        B OCTOSPI2_IRQHandler
+
+       PUBWEAK TSC_IRQHandler
+       SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+       B TSC_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK I2C4_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_ER_IRQHandler
+        B I2C4_ER_IRQHandler
+
+        PUBWEAK I2C4_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_EV_IRQHandler
+        B I2C4_EV_IRQHandler
+
+        PUBWEAK DMA2D_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2D_IRQHandler
+        B DMA2D_IRQHandler
+
+        PUBWEAK DCMI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DCMI_IRQHandler
+        B DCMI_IRQHandler
+
+        PUBWEAK LTDC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_IRQHandler
+        B LTDC_IRQHandler
+
+        PUBWEAK LTDC_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_ER_IRQHandler
+        B LTDC_ER_IRQHandler
+
+        PUBWEAK GFXMMU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GFXMMU_IRQHandler
+        B GFXMMU_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

CMSIS/STM32L4xx/Source/Templates/iar/startup_stm32l4r9xx.s

@@ -0,0 +1,674 @@
+;********************************************************************************
+;* File Name          : startup_stm32l4r9xx.s
+;* Author             : MCD Application Team
+;* Description        : STM32L4R9xx Ultra Low Power Devices vector
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler             ; Reset Handler
+
+        DCD     NMI_Handler               ; NMI Handler
+        DCD     HardFault_Handler         ; Hard Fault Handler
+        DCD     MemManage_Handler         ; MPU Fault Handler
+        DCD     BusFault_Handler          ; Bus Fault Handler
+        DCD     UsageFault_Handler        ; Usage Fault Handler
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     SVC_Handler               ; SVCall Handler
+        DCD     DebugMon_Handler          ; Debug Monitor Handler
+        DCD     0                         ; Reserved
+        DCD     PendSV_Handler            ; PendSV Handler
+        DCD     SysTick_Handler           ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
+        DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+        DCD     FLASH_IRQHandler                  ; FLASH
+        DCD     RCC_IRQHandler                    ; RCC
+        DCD     EXTI0_IRQHandler                  ; EXTI Line0
+        DCD     EXTI1_IRQHandler                  ; EXTI Line1
+        DCD     EXTI2_IRQHandler                  ; EXTI Line2
+        DCD     EXTI3_IRQHandler                  ; EXTI Line3
+        DCD     EXTI4_IRQHandler                  ; EXTI Line4
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7
+        DCD     ADC1_IRQHandler                   ; ADC1
+        DCD     CAN1_TX_IRQHandler                ; CAN1 TX
+        DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0
+        DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1
+        DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE
+        DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+        DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Commutation and TIM17
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+        DCD     TIM2_IRQHandler                   ; TIM2
+        DCD     TIM3_IRQHandler                   ; TIM3
+        DCD     TIM4_IRQHandler                   ; TIM4
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+        DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+        DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+        DCD     SPI1_IRQHandler                   ; SPI1
+        DCD     SPI2_IRQHandler                   ; SPI2
+        DCD     USART1_IRQHandler                 ; USART1
+        DCD     USART2_IRQHandler                 ; USART2
+        DCD     USART3_IRQHandler                 ; USART3
+        DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+        DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM1 Filter 3 global Interrupt
+        DCD     TIM8_BRK_IRQHandler               ; TIM8 Break Interrupt
+        DCD     TIM8_UP_IRQHandler                ; TIM8 Update Interrupt
+        DCD     TIM8_TRG_COM_IRQHandler           ; TIM8 Trigger and Commutation Interrupt
+        DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt
+        DCD     0                                 ; Reserved
+        DCD     FMC_IRQHandler                    ; FMC
+        DCD     SDMMC1_IRQHandler                 ; SDMMC1
+        DCD     TIM5_IRQHandler                   ; TIM5
+        DCD     SPI3_IRQHandler                   ; SPI3
+        DCD     UART4_IRQHandler                  ; UART4
+        DCD     UART5_IRQHandler                  ; UART5
+        DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+        DCD     TIM7_IRQHandler                   ; TIM7
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5
+        DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM1 Filter 0 global Interrupt
+        DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM1 Filter 1 global Interrupt
+        DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM1 Filter 2 global Interrupt
+        DCD     COMP_IRQHandler                   ; COMP Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LP TIM1 interrupt
+        DCD     LPTIM2_IRQHandler                 ; LP TIM2 interrupt
+        DCD     OTG_FS_IRQHandler                 ; USB OTG FS
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7
+        DCD     LPUART1_IRQHandler                ; LP UART 1 interrupt
+        DCD     OCTOSPI1_IRQHandler               ; OctoSPI1 global interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 event
+        DCD     I2C3_ER_IRQHandler                ; I2C3 error
+        DCD     SAI1_IRQHandler                   ; Serial Audio Interface 1 global interrupt
+        DCD     SAI2_IRQHandler                   ; Serial Audio Interface 2 global interrupt
+        DCD     OCTOSPI2_IRQHandler               ; OctoSPI2 global interrupt
+        DCD     TSC_IRQHandler                    ; Touch Sense Controller global interrupt
+        DCD     DSI_IRQHandler                    ; DSI global interrupt
+        DCD     0                                 ; Reserved
+        DCD     RNG_IRQHandler                    ; RNG global interrupt
+        DCD     FPU_IRQHandler                    ; FPU
+        DCD     CRS_IRQHandler                    ; CRS interrupt
+        DCD     I2C4_ER_IRQHandler                ; I2C4 error
+        DCD     I2C4_EV_IRQHandler                ; I2C4 event
+        DCD     DCMI_IRQHandler                   ; DCMI global interrupt
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     DMA2D_IRQHandler                  ; DMA2D global interrupt
+        DCD     LTDC_IRQHandler                   ; LTDC global interrupt
+        DCD     LTDC_ER_IRQHandler                ; LTDC error global interrupt
+        DCD     GFXMMU_IRQHandler                 ; GFXMMU global interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX1 overrun global interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_IRQHandler
+        B TAMP_STAMP_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK CAN1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_TX_IRQHandler
+        B CAN1_TX_IRQHandler
+
+        PUBWEAK CAN1_RX0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_RX0_IRQHandler
+        B CAN1_RX0_IRQHandler
+
+        PUBWEAK CAN1_RX1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_RX1_IRQHandler
+        B CAN1_RX1_IRQHandler
+
+        PUBWEAK CAN1_SCE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_SCE_IRQHandler
+        B CAN1_SCE_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_TIM15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_TIM15_IRQHandler
+        B TIM1_BRK_TIM15_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+        B TIM3_IRQHandler
+
+        PUBWEAK TIM4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+        B TIM4_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+        B I2C2_EV_IRQHandler
+
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+        B I2C2_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+        B USART3_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK DFSDM1_FLT3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT3_IRQHandler
+        B DFSDM1_FLT3_IRQHandler
+
+        PUBWEAK TIM8_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_IRQHandler
+        B TIM8_BRK_IRQHandler
+
+        PUBWEAK TIM8_UP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_IRQHandler
+        B TIM8_UP_IRQHandler
+
+        PUBWEAK TIM8_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_IRQHandler
+        B TIM8_TRG_COM_IRQHandler
+
+        PUBWEAK TIM8_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+        B TIM8_CC_IRQHandler
+
+        PUBWEAK FMC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+        B FMC_IRQHandler
+
+        PUBWEAK SDMMC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+        B SDMMC1_IRQHandler
+
+        PUBWEAK TIM5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+        B TIM5_IRQHandler
+
+        PUBWEAK SPI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+        B SPI3_IRQHandler
+
+        PUBWEAK UART4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+        B UART4_IRQHandler
+
+        PUBWEAK UART5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+        B UART5_IRQHandler
+
+        PUBWEAK TIM6_DAC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+        B TIM6_DAC_IRQHandler
+
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+        B TIM7_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DFSDM1_FLT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT0_IRQHandler
+        B DFSDM1_FLT0_IRQHandler
+
+        PUBWEAK DFSDM1_FLT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT1_IRQHandler
+        B DFSDM1_FLT1_IRQHandler
+
+        PUBWEAK DFSDM1_FLT2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT2_IRQHandler
+        B DFSDM1_FLT2_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK OTG_FS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_IRQHandler
+        B OTG_FS_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK OCTOSPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI1_IRQHandler
+        B OCTOSPI1_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SAI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+        B SAI1_IRQHandler
+
+       PUBWEAK SAI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SAI2_IRQHandler
+        B SAI2_IRQHandler
+
+        PUBWEAK OCTOSPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI2_IRQHandler
+        B OCTOSPI2_IRQHandler
+
+       PUBWEAK TSC_IRQHandler
+       SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+       B TSC_IRQHandler
+
+       PUBWEAK DSI_IRQHandler
+       SECTION .text:CODE:NOROOT:REORDER(1)
+DSI_IRQHandler
+       B DSI_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK I2C4_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_ER_IRQHandler
+        B I2C4_ER_IRQHandler
+
+        PUBWEAK I2C4_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_EV_IRQHandler
+        B I2C4_EV_IRQHandler
+
+        PUBWEAK DMA2D_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2D_IRQHandler
+        B DMA2D_IRQHandler
+
+        PUBWEAK DCMI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DCMI_IRQHandler
+        B DCMI_IRQHandler
+
+        PUBWEAK LTDC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_IRQHandler
+        B LTDC_IRQHandler
+
+        PUBWEAK LTDC_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_ER_IRQHandler
+        B LTDC_ER_IRQHandler
+
+        PUBWEAK GFXMMU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GFXMMU_IRQHandler
+        B GFXMMU_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

CMSIS/STM32L4xx/Source/Templates/iar/startup_stm32l4s5xx.s

@@ -0,0 +1,674 @@
+;********************************************************************************
+;* File Name          : startup_stm32l4s5xx.s
+;* Author             : MCD Application Team
+;* Description        : STM32L4S5xx Ultra Low Power Devices vector
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler             ; Reset Handler
+
+        DCD     NMI_Handler               ; NMI Handler
+        DCD     HardFault_Handler         ; Hard Fault Handler
+        DCD     MemManage_Handler         ; MPU Fault Handler
+        DCD     BusFault_Handler          ; Bus Fault Handler
+        DCD     UsageFault_Handler        ; Usage Fault Handler
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     SVC_Handler               ; SVCall Handler
+        DCD     DebugMon_Handler          ; Debug Monitor Handler
+        DCD     0                         ; Reserved
+        DCD     PendSV_Handler            ; PendSV Handler
+        DCD     SysTick_Handler           ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
+        DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+        DCD     FLASH_IRQHandler                  ; FLASH
+        DCD     RCC_IRQHandler                    ; RCC
+        DCD     EXTI0_IRQHandler                  ; EXTI Line0
+        DCD     EXTI1_IRQHandler                  ; EXTI Line1
+        DCD     EXTI2_IRQHandler                  ; EXTI Line2
+        DCD     EXTI3_IRQHandler                  ; EXTI Line3
+        DCD     EXTI4_IRQHandler                  ; EXTI Line4
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7
+        DCD     ADC1_IRQHandler                   ; ADC1
+        DCD     CAN1_TX_IRQHandler                ; CAN1 TX
+        DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0
+        DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1
+        DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE
+        DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+        DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Commutation and TIM17
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+        DCD     TIM2_IRQHandler                   ; TIM2
+        DCD     TIM3_IRQHandler                   ; TIM3
+        DCD     TIM4_IRQHandler                   ; TIM4
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+        DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+        DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+        DCD     SPI1_IRQHandler                   ; SPI1
+        DCD     SPI2_IRQHandler                   ; SPI2
+        DCD     USART1_IRQHandler                 ; USART1
+        DCD     USART2_IRQHandler                 ; USART2
+        DCD     USART3_IRQHandler                 ; USART3
+        DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+        DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM1 Filter 3 global Interrupt
+        DCD     TIM8_BRK_IRQHandler               ; TIM8 Break Interrupt
+        DCD     TIM8_UP_IRQHandler                ; TIM8 Update Interrupt
+        DCD     TIM8_TRG_COM_IRQHandler           ; TIM8 Trigger and Commutation Interrupt
+        DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt
+        DCD     0                                 ; Reserved
+        DCD     FMC_IRQHandler                    ; FMC
+        DCD     SDMMC1_IRQHandler                 ; SDMMC1
+        DCD     TIM5_IRQHandler                   ; TIM5
+        DCD     SPI3_IRQHandler                   ; SPI3
+        DCD     UART4_IRQHandler                  ; UART4
+        DCD     UART5_IRQHandler                  ; UART5
+        DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+        DCD     TIM7_IRQHandler                   ; TIM7
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5
+        DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM1 Filter 0 global Interrupt
+        DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM1 Filter 1 global Interrupt
+        DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM1 Filter 2 global Interrupt
+        DCD     COMP_IRQHandler                   ; COMP Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LP TIM1 interrupt
+        DCD     LPTIM2_IRQHandler                 ; LP TIM2 interrupt
+        DCD     OTG_FS_IRQHandler                 ; USB OTG FS
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7
+        DCD     LPUART1_IRQHandler                ; LP UART 1 interrupt
+        DCD     OCTOSPI1_IRQHandler               ; OctoSPI1 global interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 event
+        DCD     I2C3_ER_IRQHandler                ; I2C3 error
+        DCD     SAI1_IRQHandler                   ; Serial Audio Interface 1 global interrupt
+        DCD     SAI2_IRQHandler                   ; Serial Audio Interface 2 global interrupt
+        DCD     OCTOSPI2_IRQHandler               ; OctoSPI2 global interrupt
+        DCD     TSC_IRQHandler                    ; Touch Sense Controller global interrupt
+        DCD     0                                 ; Reserved
+        DCD     AES_IRQHandler                    ; AES global interrupt
+        DCD     RNG_IRQHandler                    ; RNG global interrupt
+        DCD     FPU_IRQHandler                    ; FPU
+        DCD     HASH_CRS_IRQHandler               ; HASH and CRS interrupt
+        DCD     I2C4_ER_IRQHandler                ; I2C4 error
+        DCD     I2C4_EV_IRQHandler                ; I2C4 event
+        DCD     DCMI_IRQHandler                   ; DCMI global interrupt
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     DMA2D_IRQHandler                  ; DMA2D global interrupt
+        DCD     LTDC_IRQHandler                   ; LTDC global interrupt
+        DCD     LTDC_ER_IRQHandler                ; LTDC error global interrupt
+        DCD     GFXMMU_IRQHandler                 ; GFXMMU global interrupt
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX1 overrun global interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_IRQHandler
+        B TAMP_STAMP_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK CAN1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_TX_IRQHandler
+        B CAN1_TX_IRQHandler
+
+        PUBWEAK CAN1_RX0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_RX0_IRQHandler
+        B CAN1_RX0_IRQHandler
+
+        PUBWEAK CAN1_RX1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_RX1_IRQHandler
+        B CAN1_RX1_IRQHandler
+
+        PUBWEAK CAN1_SCE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_SCE_IRQHandler
+        B CAN1_SCE_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_TIM15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_TIM15_IRQHandler
+        B TIM1_BRK_TIM15_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+        B TIM3_IRQHandler
+
+        PUBWEAK TIM4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+        B TIM4_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+        B I2C2_EV_IRQHandler
+
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+        B I2C2_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+        B USART3_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK DFSDM1_FLT3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT3_IRQHandler
+        B DFSDM1_FLT3_IRQHandler
+
+        PUBWEAK TIM8_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_IRQHandler
+        B TIM8_BRK_IRQHandler
+
+        PUBWEAK TIM8_UP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_IRQHandler
+        B TIM8_UP_IRQHandler
+
+        PUBWEAK TIM8_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_IRQHandler
+        B TIM8_TRG_COM_IRQHandler
+
+        PUBWEAK TIM8_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+        B TIM8_CC_IRQHandler
+
+        PUBWEAK FMC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+        B FMC_IRQHandler
+
+        PUBWEAK SDMMC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+        B SDMMC1_IRQHandler
+
+        PUBWEAK TIM5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+        B TIM5_IRQHandler
+
+        PUBWEAK SPI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+        B SPI3_IRQHandler
+
+        PUBWEAK UART4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+        B UART4_IRQHandler
+
+        PUBWEAK UART5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+        B UART5_IRQHandler
+
+        PUBWEAK TIM6_DAC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+        B TIM6_DAC_IRQHandler
+
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+        B TIM7_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DFSDM1_FLT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT0_IRQHandler
+        B DFSDM1_FLT0_IRQHandler
+
+        PUBWEAK DFSDM1_FLT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT1_IRQHandler
+        B DFSDM1_FLT1_IRQHandler
+
+        PUBWEAK DFSDM1_FLT2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT2_IRQHandler
+        B DFSDM1_FLT2_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK OTG_FS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_IRQHandler
+        B OTG_FS_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK OCTOSPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI1_IRQHandler
+        B OCTOSPI1_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SAI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+        B SAI1_IRQHandler
+
+       PUBWEAK SAI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SAI2_IRQHandler
+        B SAI2_IRQHandler
+
+        PUBWEAK OCTOSPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI2_IRQHandler
+        B OCTOSPI2_IRQHandler
+
+       PUBWEAK TSC_IRQHandler
+       SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+       B TSC_IRQHandler
+
+        PUBWEAK AES_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES_IRQHandler
+        B AES_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK HASH_CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HASH_CRS_IRQHandler
+        B HASH_CRS_IRQHandler
+
+        PUBWEAK I2C4_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_ER_IRQHandler
+        B I2C4_ER_IRQHandler
+
+        PUBWEAK I2C4_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_EV_IRQHandler
+        B I2C4_EV_IRQHandler
+
+        PUBWEAK DMA2D_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2D_IRQHandler
+        B DMA2D_IRQHandler
+
+        PUBWEAK DCMI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DCMI_IRQHandler
+        B DCMI_IRQHandler
+
+        PUBWEAK LTDC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_IRQHandler
+        B LTDC_IRQHandler
+
+        PUBWEAK LTDC_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_ER_IRQHandler
+        B LTDC_ER_IRQHandler
+
+        PUBWEAK GFXMMU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GFXMMU_IRQHandler
+        B GFXMMU_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/