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Import STM32Cube_FW_L4_V1.8.1 on 16-Jun-2017

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This commit is contained in:
Damien George 2017-08-29 14:07:43 +10:00
parent 0496e4f557
commit 540ae5c50a
201 changed files with 794 additions and 702 deletions
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16
CMSIS/STM32L4xx/Include/stm32l431xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l431xx.h
* @author MCD Application Team
* @version V1.3.1
* @date 21-April-2017
* @version V1.3.2
* @date 16-June-2017
* @brief CMSIS STM32L431xx Device Peripheral Access Layer Header File.
*
* This file contains:
@ -945,7 +945,6 @@ typedef struct
#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
#define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
/* Legacy defines */
@ -6787,11 +6786,8 @@ typedef struct
#define EXTI_IMR2_IM38_Pos (6U)
#define EXTI_IMR2_IM38_Msk (0x1U << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
#define EXTI_IMR2_IM39_Pos (7U)
#define EXTI_IMR2_IM39_Msk (0x1U << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
#define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0xFFU << EXTI_IMR2_IM_Pos) /*!< 0x000000FF */
#define EXTI_IMR2_IM_Msk (0x7FU << EXTI_IMR2_IM_Pos) /*!< 0x0000007F */
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
/******************* Bit definition for EXTI_EMR2 register ******************/
@ -6816,9 +6812,9 @@ typedef struct
#define EXTI_EMR2_EM38_Pos (6U)
#define EXTI_EMR2_EM38_Msk (0x1U << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
#define EXTI_EMR2_EM39_Pos (7U)
#define EXTI_EMR2_EM39_Msk (0x1U << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0x7FU << EXTI_EMR2_EM_Pos) /*!< 0x0000007F */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
/****************** Bit definition for EXTI_RTSR2 register ******************/
#define EXTI_RTSR2_RT35_Pos (3U)

22
CMSIS/STM32L4xx/Include/stm32l432xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l432xx.h
* @author MCD Application Team
* @version V1.3.1
* @date 21-April-2017
* @version V1.3.2
* @date 16-June-2017
* @brief CMSIS STM32L432xx Device Peripheral Access Layer Header File.
*
* This file contains:
@ -941,7 +941,6 @@ typedef struct
#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
#define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
/* Legacy defines */
@ -6763,20 +6762,14 @@ typedef struct
#define EXTI_IMR2_IM35_Pos (3U)
#define EXTI_IMR2_IM35_Msk (0x1U << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
#define EXTI_IMR2_IM36_Pos (4U)
#define EXTI_IMR2_IM36_Msk (0x1U << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
#define EXTI_IMR2_IM37_Pos (5U)
#define EXTI_IMR2_IM37_Msk (0x1U << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
#define EXTI_IMR2_IM38_Pos (6U)
#define EXTI_IMR2_IM38_Msk (0x1U << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
#define EXTI_IMR2_IM39_Pos (7U)
#define EXTI_IMR2_IM39_Msk (0x1U << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
#define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0xFFU << EXTI_IMR2_IM_Pos) /*!< 0x000000FF */
#define EXTI_IMR2_IM_Msk (0x6FU << EXTI_IMR2_IM_Pos) /*!< 0x0000006F */
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
/******************* Bit definition for EXTI_EMR2 register ******************/
@ -6792,18 +6785,15 @@ typedef struct
#define EXTI_EMR2_EM35_Pos (3U)
#define EXTI_EMR2_EM35_Msk (0x1U << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */
#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35 */
#define EXTI_EMR2_EM36_Pos (4U)
#define EXTI_EMR2_EM36_Msk (0x1U << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */
#define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36 */
#define EXTI_EMR2_EM37_Pos (5U)
#define EXTI_EMR2_EM37_Msk (0x1U << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37 */
#define EXTI_EMR2_EM38_Pos (6U)
#define EXTI_EMR2_EM38_Msk (0x1U << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
#define EXTI_EMR2_EM39_Pos (7U)
#define EXTI_EMR2_EM39_Msk (0x1U << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0x6FU << EXTI_EMR2_EM_Pos) /*!< 0x0000006F */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
/****************** Bit definition for EXTI_RTSR2 register ******************/
#define EXTI_RTSR2_RT35_Pos (3U)

8
CMSIS/STM32L4xx/Include/stm32l433xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l433xx.h
* @author MCD Application Team
* @version V1.3.1
* @date 21-April-2017
* @version V1.3.2
* @date 16-June-2017
* @brief CMSIS STM32L433xx Device Peripheral Access Layer Header File.
*
* This file contains:
@ -999,7 +999,6 @@ typedef struct
#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
#define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
/* Legacy defines */
@ -6878,6 +6877,9 @@ typedef struct
#define EXTI_EMR2_EM39_Pos (7U)
#define EXTI_EMR2_EM39_Msk (0x1U << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0xFFU << EXTI_EMR2_EM_Pos) /*!< 0x000000FF */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
/****************** Bit definition for EXTI_RTSR2 register ******************/
#define EXTI_RTSR2_RT35_Pos (3U)

19
CMSIS/STM32L4xx/Include/stm32l442xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l442xx.h
* @author MCD Application Team
* @version V1.3.1
* @date 21-April-2017
* @version V1.3.2
* @date 16-June-2017
* @brief CMSIS STM32L442xx Device Peripheral Access Layer Header File.
*
* This file contains:
@ -974,7 +974,6 @@ typedef struct
#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
#define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
/* Legacy defines */
@ -6979,20 +6978,14 @@ typedef struct
#define EXTI_IMR2_IM35_Pos (3U)
#define EXTI_IMR2_IM35_Msk (0x1U << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
#define EXTI_IMR2_IM36_Pos (4U)
#define EXTI_IMR2_IM36_Msk (0x1U << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
#define EXTI_IMR2_IM37_Pos (5U)
#define EXTI_IMR2_IM37_Msk (0x1U << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
#define EXTI_IMR2_IM38_Pos (6U)
#define EXTI_IMR2_IM38_Msk (0x1U << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
#define EXTI_IMR2_IM39_Pos (7U)
#define EXTI_IMR2_IM39_Msk (0x1U << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
#define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0xFFU << EXTI_IMR2_IM_Pos) /*!< 0x000000FF */
#define EXTI_IMR2_IM_Msk (0x6FU << EXTI_IMR2_IM_Pos) /*!< 0x0000006F */
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
/******************* Bit definition for EXTI_EMR2 register ******************/
@ -7017,9 +7010,9 @@ typedef struct
#define EXTI_EMR2_EM38_Pos (6U)
#define EXTI_EMR2_EM38_Msk (0x1U << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
#define EXTI_EMR2_EM39_Pos (7U)
#define EXTI_EMR2_EM39_Msk (0x1U << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0x7FU << EXTI_EMR2_EM_Pos) /*!< 0x0000007F */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
/****************** Bit definition for EXTI_RTSR2 register ******************/
#define EXTI_RTSR2_RT35_Pos (3U)

8
CMSIS/STM32L4xx/Include/stm32l443xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l443xx.h
* @author MCD Application Team
* @version V1.3.1
* @date 21-April-2017
* @version V1.3.2
* @date 16-June-2017
* @brief CMSIS STM32L443xx Device Peripheral Access Layer Header File.
*
* This file contains:
@ -1032,7 +1032,6 @@ typedef struct
#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
#define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
/* Legacy defines */
@ -7094,6 +7093,9 @@ typedef struct
#define EXTI_EMR2_EM39_Pos (7U)
#define EXTI_EMR2_EM39_Msk (0x1U << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0xFFU << EXTI_EMR2_EM_Pos) /*!< 0x000000FF */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
/****************** Bit definition for EXTI_RTSR2 register ******************/
#define EXTI_RTSR2_RT35_Pos (3U)

28
CMSIS/STM32L4xx/Include/stm32l451xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l451xx.h
* @author MCD Application Team
* @version V1.3.1
* @date 21-April-2017
* @version V1.3.2
* @date 16-June-2017
* @brief CMSIS STM32L451xx Device Peripheral Access Layer Header File.
*
* This file contains:
@ -965,7 +965,6 @@ typedef struct
#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
#define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
/* Legacy defines */
@ -7029,9 +7028,6 @@ typedef struct
#define EXTI_IMR2_IM33_Pos (1U)
#define EXTI_IMR2_IM33_Msk (0x1U << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */
#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< Interrupt Mask on line 33 */
#define EXTI_IMR2_IM34_Pos (2U)
#define EXTI_IMR2_IM34_Msk (0x1U << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */
#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< Interrupt Mask on line 34 */
#define EXTI_IMR2_IM35_Pos (3U)
#define EXTI_IMR2_IM35_Msk (0x1U << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
@ -7044,14 +7040,11 @@ typedef struct
#define EXTI_IMR2_IM38_Pos (6U)
#define EXTI_IMR2_IM38_Msk (0x1U << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
#define EXTI_IMR2_IM39_Pos (7U)
#define EXTI_IMR2_IM39_Msk (0x1U << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
#define EXTI_IMR2_IM40_Pos (8U)
#define EXTI_IMR2_IM40_Msk (0x1U << EXTI_IMR2_IM40_Pos) /*!< 0x00000100 */
#define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk /*!< Interrupt Mask on line 40 */
#define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0x1FFU << EXTI_IMR2_IM_Pos) /*!< 0x000001FF */
#define EXTI_IMR2_IM_Msk (0x16BU << EXTI_IMR2_IM_Pos) /*!< 0x0000016B */
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
/******************* Bit definition for EXTI_EMR2 register ******************/
@ -7061,9 +7054,6 @@ typedef struct
#define EXTI_EMR2_EM33_Pos (1U)
#define EXTI_EMR2_EM33_Msk (0x1U << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */
#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33 */
#define EXTI_EMR2_EM34_Pos (2U)
#define EXTI_EMR2_EM34_Msk (0x1U << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */
#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< Event Mask on line 34 */
#define EXTI_EMR2_EM35_Pos (3U)
#define EXTI_EMR2_EM35_Msk (0x1U << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */
#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35 */
@ -7076,12 +7066,12 @@ typedef struct
#define EXTI_EMR2_EM38_Pos (6U)
#define EXTI_EMR2_EM38_Msk (0x1U << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
#define EXTI_EMR2_EM39_Pos (7U)
#define EXTI_EMR2_EM39_Msk (0x1U << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
#define EXTI_EMR2_IM40_Pos (8U)
#define EXTI_EMR2_IM40_Msk (0x1U << EXTI_EMR2_IM40_Pos) /*!< 0x00000100 */
#define EXTI_EMR2_IM40 EXTI_EMR2_IM40_Msk /*!< Event Mask on line 40 */
#define EXTI_EMR2_EM40_Pos (8U)
#define EXTI_EMR2_EM40_Msk (0x1U << EXTI_EMR2_EM40_Pos) /*!< 0x00000100 */
#define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk /*!< Event Mask on line 40 */
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0x17BU << EXTI_EMR2_EM_Pos) /*!< 0x0000017B */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
/****************** Bit definition for EXTI_RTSR2 register ******************/
#define EXTI_RTSR2_RT35_Pos (3U)

34
CMSIS/STM32L4xx/Include/stm32l452xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l452xx.h
* @author MCD Application Team
* @version V1.3.1
* @date 21-April-2017
* @version V1.3.2
* @date 16-June-2017
* @brief CMSIS STM32L452xx Device Peripheral Access Layer Header File.
*
* This file contains:
@ -1004,7 +1004,6 @@ typedef struct
#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
#define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
/* Legacy defines */
@ -7071,29 +7070,20 @@ typedef struct
#define EXTI_IMR2_IM33_Pos (1U)
#define EXTI_IMR2_IM33_Msk (0x1U << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */
#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< Interrupt Mask on line 33 */
#define EXTI_IMR2_IM34_Pos (2U)
#define EXTI_IMR2_IM34_Msk (0x1U << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */
#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< Interrupt Mask on line 34 */
#define EXTI_IMR2_IM35_Pos (3U)
#define EXTI_IMR2_IM35_Msk (0x1U << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
#define EXTI_IMR2_IM36_Pos (4U)
#define EXTI_IMR2_IM36_Msk (0x1U << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
#define EXTI_IMR2_IM37_Pos (5U)
#define EXTI_IMR2_IM37_Msk (0x1U << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
#define EXTI_IMR2_IM38_Pos (6U)
#define EXTI_IMR2_IM38_Msk (0x1U << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
#define EXTI_IMR2_IM39_Pos (7U)
#define EXTI_IMR2_IM39_Msk (0x1U << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
#define EXTI_IMR2_IM40_Pos (8U)
#define EXTI_IMR2_IM40_Msk (0x1U << EXTI_IMR2_IM40_Pos) /*!< 0x00000100 */
#define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk /*!< Interrupt Mask on line 40 */
#define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0x1FFU << EXTI_IMR2_IM_Pos) /*!< 0x000001FF */
#define EXTI_IMR2_IM_Msk (0x16BU << EXTI_IMR2_IM_Pos) /*!< 0x0000016B */
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
/******************* Bit definition for EXTI_EMR2 register ******************/
@ -7103,27 +7093,21 @@ typedef struct
#define EXTI_EMR2_EM33_Pos (1U)
#define EXTI_EMR2_EM33_Msk (0x1U << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */
#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33 */
#define EXTI_EMR2_EM34_Pos (2U)
#define EXTI_EMR2_EM34_Msk (0x1U << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */
#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< Event Mask on line 34 */
#define EXTI_EMR2_EM35_Pos (3U)
#define EXTI_EMR2_EM35_Msk (0x1U << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */
#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35 */
#define EXTI_EMR2_EM36_Pos (4U)
#define EXTI_EMR2_EM36_Msk (0x1U << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */
#define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36 */
#define EXTI_EMR2_EM37_Pos (5U)
#define EXTI_EMR2_EM37_Msk (0x1U << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37 */
#define EXTI_EMR2_EM38_Pos (6U)
#define EXTI_EMR2_EM38_Msk (0x1U << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
#define EXTI_EMR2_EM39_Pos (7U)
#define EXTI_EMR2_EM39_Msk (0x1U << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
#define EXTI_EMR2_IM40_Pos (8U)
#define EXTI_EMR2_IM40_Msk (0x1U << EXTI_EMR2_IM40_Pos) /*!< 0x00000100 */
#define EXTI_EMR2_IM40 EXTI_EMR2_IM40_Msk /*!< Event Mask on line 40 */
#define EXTI_EMR2_EM40_Pos (8U)
#define EXTI_EMR2_EM40_Msk (0x1U << EXTI_EMR2_EM40_Pos) /*!< 0x00000100 */
#define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk /*!< Event Mask on line 40 */
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0x16BU << EXTI_EMR2_EM_Pos) /*!< 0x0000016B */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
/****************** Bit definition for EXTI_RTSR2 register ******************/
#define EXTI_RTSR2_RT35_Pos (3U)

34
CMSIS/STM32L4xx/Include/stm32l462xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l462xx.h
* @author MCD Application Team
* @version V1.3.1
* @date 21-April-2017
* @version V1.3.2
* @date 16-June-2017
* @brief CMSIS STM32L462xx Device Peripheral Access Layer Header File.
*
* This file contains:
@ -1037,7 +1037,6 @@ typedef struct
#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
#define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
/* Legacy defines */
@ -7287,29 +7286,20 @@ typedef struct
#define EXTI_IMR2_IM33_Pos (1U)
#define EXTI_IMR2_IM33_Msk (0x1U << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */
#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< Interrupt Mask on line 33 */
#define EXTI_IMR2_IM34_Pos (2U)
#define EXTI_IMR2_IM34_Msk (0x1U << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */
#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< Interrupt Mask on line 34 */
#define EXTI_IMR2_IM35_Pos (3U)
#define EXTI_IMR2_IM35_Msk (0x1U << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
#define EXTI_IMR2_IM36_Pos (4U)
#define EXTI_IMR2_IM36_Msk (0x1U << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
#define EXTI_IMR2_IM37_Pos (5U)
#define EXTI_IMR2_IM37_Msk (0x1U << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
#define EXTI_IMR2_IM38_Pos (6U)
#define EXTI_IMR2_IM38_Msk (0x1U << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
#define EXTI_IMR2_IM39_Pos (7U)
#define EXTI_IMR2_IM39_Msk (0x1U << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
#define EXTI_IMR2_IM40_Pos (8U)
#define EXTI_IMR2_IM40_Msk (0x1U << EXTI_IMR2_IM40_Pos) /*!< 0x00000100 */
#define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk /*!< Interrupt Mask on line 40 */
#define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0x1FFU << EXTI_IMR2_IM_Pos) /*!< 0x000001FF */
#define EXTI_IMR2_IM_Msk (0x16BU << EXTI_IMR2_IM_Pos) /*!< 0x0000016B */
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
/******************* Bit definition for EXTI_EMR2 register ******************/
@ -7319,27 +7309,21 @@ typedef struct
#define EXTI_EMR2_EM33_Pos (1U)
#define EXTI_EMR2_EM33_Msk (0x1U << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */
#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33 */
#define EXTI_EMR2_EM34_Pos (2U)
#define EXTI_EMR2_EM34_Msk (0x1U << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */
#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< Event Mask on line 34 */
#define EXTI_EMR2_EM35_Pos (3U)
#define EXTI_EMR2_EM35_Msk (0x1U << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */
#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35 */
#define EXTI_EMR2_EM36_Pos (4U)
#define EXTI_EMR2_EM36_Msk (0x1U << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */
#define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36 */
#define EXTI_EMR2_EM37_Pos (5U)
#define EXTI_EMR2_EM37_Msk (0x1U << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37 */
#define EXTI_EMR2_EM38_Pos (6U)
#define EXTI_EMR2_EM38_Msk (0x1U << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
#define EXTI_EMR2_EM39_Pos (7U)
#define EXTI_EMR2_EM39_Msk (0x1U << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
#define EXTI_EMR2_IM40_Pos (8U)
#define EXTI_EMR2_IM40_Msk (0x1U << EXTI_EMR2_IM40_Pos) /*!< 0x00000100 */
#define EXTI_EMR2_IM40 EXTI_EMR2_IM40_Msk /*!< Event Mask on line 40 */
#define EXTI_EMR2_EM40_Pos (8U)
#define EXTI_EMR2_EM40_Msk (0x1U << EXTI_EMR2_EM40_Pos) /*!< 0x00000100 */
#define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk /*!< Event Mask on line 40 */
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0x16BU << EXTI_EMR2_EM_Pos) /*!< 0x0000016B */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
/****************** Bit definition for EXTI_RTSR2 register ******************/
#define EXTI_RTSR2_RT35_Pos (3U)

19
CMSIS/STM32L4xx/Include/stm32l471xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l471xx.h
* @author MCD Application Team
* @version V1.3.1
* @date 21-April-2017
* @version V1.3.2
* @date 16-June-2017
* @brief CMSIS STM32L471xx Device Peripheral Access Layer Header File.
*
* This file contains:
@ -1021,7 +1021,6 @@ typedef struct
#define FMC_R_BASE ((uint32_t)0xA0000000U) /*!< FMC control registers base address */
#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
#define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
/* Legacy defines */
@ -7294,11 +7293,8 @@ typedef struct
#define EXTI_IMR2_IM38_Pos (6U)
#define EXTI_IMR2_IM38_Msk (0x1U << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
#define EXTI_IMR2_IM39_Pos (7U)
#define EXTI_IMR2_IM39_Msk (0x1U << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
#define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0xFFU << EXTI_IMR2_IM_Pos) /*!< 0x000000FF */
#define EXTI_IMR2_IM_Msk (0x7FU << EXTI_IMR2_IM_Pos) /*!< 0x0000007F */
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
/******************* Bit definition for EXTI_EMR2 register ******************/
@ -7323,9 +7319,9 @@ typedef struct
#define EXTI_EMR2_EM38_Pos (6U)
#define EXTI_EMR2_EM38_Msk (0x1U << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
#define EXTI_EMR2_EM39_Pos (7U)
#define EXTI_EMR2_EM39_Msk (0x1U << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0x7FU << EXTI_EMR2_EM_Pos) /*!< 0x0000007F */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
/****************** Bit definition for EXTI_RTSR2 register ******************/
#define EXTI_RTSR2_RT35_Pos (3U)
@ -16648,7 +16644,8 @@ typedef struct
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5))
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8))
/**************** TIM Instances : external trigger input available ************/
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \

19
CMSIS/STM32L4xx/Include/stm32l475xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l475xx.h
* @author MCD Application Team
* @version V1.3.1
* @date 21-April-2017
* @version V1.3.2
* @date 16-June-2017
* @brief CMSIS STM32L475xx Device Peripheral Access Layer Header File.
*
* This file contains:
@ -1140,7 +1140,6 @@ typedef struct
#define FMC_R_BASE ((uint32_t)0xA0000000U) /*!< FMC control registers base address */
#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
#define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
/* Legacy defines */
@ -7431,11 +7430,8 @@ typedef struct
#define EXTI_IMR2_IM38_Pos (6U)
#define EXTI_IMR2_IM38_Msk (0x1U << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
#define EXTI_IMR2_IM39_Pos (7U)
#define EXTI_IMR2_IM39_Msk (0x1U << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
#define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0xFFU << EXTI_IMR2_IM_Pos) /*!< 0x000000FF */
#define EXTI_IMR2_IM_Msk (0x7FU << EXTI_IMR2_IM_Pos) /*!< 0x0000007F */
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
/******************* Bit definition for EXTI_EMR2 register ******************/
@ -7460,9 +7456,9 @@ typedef struct
#define EXTI_EMR2_EM38_Pos (6U)
#define EXTI_EMR2_EM38_Msk (0x1U << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
#define EXTI_EMR2_EM39_Pos (7U)
#define EXTI_EMR2_EM39_Msk (0x1U << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0x7FU << EXTI_EMR2_EM_Pos) /*!< 0x0000007F */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
/****************** Bit definition for EXTI_RTSR2 register ******************/
#define EXTI_RTSR2_RT35_Pos (3U)
@ -18167,7 +18163,8 @@ typedef struct
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5))
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8))
/**************** TIM Instances : external trigger input available ************/
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \

11
CMSIS/STM32L4xx/Include/stm32l476xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l476xx.h
* @author MCD Application Team
* @version V1.3.1
* @date 21-April-2017
* @version V1.3.2
* @date 16-June-2017
* @brief CMSIS STM32L476xx Device Peripheral Access Layer Header File.
*
* This file contains:
@ -1155,7 +1155,6 @@ typedef struct
#define FMC_R_BASE ((uint32_t)0xA0000000U) /*!< FMC control registers base address */
#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
#define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
/* Legacy defines */
@ -7480,6 +7479,9 @@ typedef struct
#define EXTI_EMR2_EM39_Pos (7U)
#define EXTI_EMR2_EM39_Msk (0x1U << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0xFFU << EXTI_EMR2_EM_Pos) /*!< 0x000000FF */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
/****************** Bit definition for EXTI_RTSR2 register ******************/
#define EXTI_RTSR2_RT35_Pos (3U)
@ -18315,7 +18317,8 @@ typedef struct
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5))
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8))
/**************** TIM Instances : external trigger input available ************/
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \

19
CMSIS/STM32L4xx/Include/stm32l485xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l485xx.h
* @author MCD Application Team
* @version V1.3.1
* @date 21-April-2017
* @version V1.3.2
* @date 16-June-2017
* @brief CMSIS STM32L485xx Device Peripheral Access Layer Header File.
*
* This file contains:
@ -1173,7 +1173,6 @@ typedef struct
#define FMC_R_BASE ((uint32_t)0xA0000000U) /*!< FMC control registers base address */
#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
#define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
/* Legacy defines */
@ -7647,11 +7646,8 @@ typedef struct
#define EXTI_IMR2_IM38_Pos (6U)
#define EXTI_IMR2_IM38_Msk (0x1U << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
#define EXTI_IMR2_IM39_Pos (7U)
#define EXTI_IMR2_IM39_Msk (0x1U << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
#define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0xFFU << EXTI_IMR2_IM_Pos) /*!< 0x000000FF */
#define EXTI_IMR2_IM_Msk (0x7FU << EXTI_IMR2_IM_Pos) /*!< 0x0000007F */
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
/******************* Bit definition for EXTI_EMR2 register ******************/
@ -7676,9 +7672,9 @@ typedef struct
#define EXTI_EMR2_EM38_Pos (6U)
#define EXTI_EMR2_EM38_Msk (0x1U << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
#define EXTI_EMR2_EM39_Pos (7U)
#define EXTI_EMR2_EM39_Msk (0x1U << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0x7FU << EXTI_EMR2_EM_Pos) /*!< 0x0000007F */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
/****************** Bit definition for EXTI_RTSR2 register ******************/
#define EXTI_RTSR2_RT35_Pos (3U)
@ -18395,7 +18391,8 @@ typedef struct
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5))
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8))
/**************** TIM Instances : external trigger input available ************/
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \

11
CMSIS/STM32L4xx/Include/stm32l486xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l486xx.h
* @author MCD Application Team
* @version V1.3.1
* @date 21-April-2017
* @version V1.3.2
* @date 16-June-2017
* @brief CMSIS STM32L486xx Device Peripheral Access Layer Header File.
*
* This file contains:
@ -1188,7 +1188,6 @@ typedef struct
#define FMC_R_BASE ((uint32_t)0xA0000000U) /*!< FMC control registers base address */
#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
#define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
/* Legacy defines */
@ -7696,6 +7695,9 @@ typedef struct
#define EXTI_EMR2_EM39_Pos (7U)
#define EXTI_EMR2_EM39_Msk (0x1U << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0xFFU << EXTI_EMR2_EM_Pos) /*!< 0x000000FF */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
/****************** Bit definition for EXTI_RTSR2 register ******************/
#define EXTI_RTSR2_RT35_Pos (3U)
@ -18543,7 +18545,8 @@ typedef struct
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5))
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8))
/**************** TIM Instances : external trigger input available ************/
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \

17
CMSIS/STM32L4xx/Include/stm32l496xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l496xx.h
* @author MCD Application Team
* @version V1.3.1
* @date 21-April-2017
* @version V1.3.2
* @date 16-June-2017
* @brief CMSIS STM32L496xx Device Peripheral Access Layer Header File.
*
* This file contains:
@ -1228,7 +1228,6 @@ typedef struct
#define FMC_R_BASE ((uint32_t)0xA0000000U) /*!< FMC control registers base address */
#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
#define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
/* Legacy defines */
@ -8318,9 +8317,12 @@ typedef struct
#define EXTI_EMR2_EM39_Pos (7U)
#define EXTI_EMR2_EM39_Msk (0x1U << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
#define EXTI_EMR2_IM40_Pos (8U)
#define EXTI_EMR2_IM40_Msk (0x1U << EXTI_EMR2_IM40_Pos) /*!< 0x00000100 */
#define EXTI_EMR2_IM40 EXTI_EMR2_IM40_Msk /*!< Event Mask on line 40 */
#define EXTI_EMR2_EM40_Pos (8U)
#define EXTI_EMR2_EM40_Msk (0x1U << EXTI_EMR2_EM40_Pos) /*!< 0x00000100 */
#define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk /*!< Event Mask on line 40 */
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0x1FFU << EXTI_EMR2_EM_Pos) /*!< 0x000001FF */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
/****************** Bit definition for EXTI_RTSR2 register ******************/
#define EXTI_RTSR2_RT35_Pos (3U)
@ -19561,7 +19563,8 @@ typedef struct
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5))
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8))
/**************** TIM Instances : external trigger input available ************/
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \

17
CMSIS/STM32L4xx/Include/stm32l4a6xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4a6xx.h
* @author MCD Application Team
* @version V1.3.1
* @date 21-April-2017
* @version V1.3.2
* @date 16-June-2017
* @brief CMSIS STM32L4A6xx Device Peripheral Access Layer Header File.
*
* This file contains:
@ -1286,7 +1286,6 @@ typedef struct
#define FMC_R_BASE ((uint32_t)0xA0000000U) /*!< FMC control registers base address */
#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
#define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
/* Legacy defines */
@ -8563,9 +8562,12 @@ typedef struct
#define EXTI_EMR2_EM39_Pos (7U)
#define EXTI_EMR2_EM39_Msk (0x1U << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
#define EXTI_EMR2_IM40_Pos (8U)
#define EXTI_EMR2_IM40_Msk (0x1U << EXTI_EMR2_IM40_Pos) /*!< 0x00000100 */
#define EXTI_EMR2_IM40 EXTI_EMR2_IM40_Msk /*!< Event Mask on line 40 */
#define EXTI_EMR2_EM40_Pos (8U)
#define EXTI_EMR2_EM40_Msk (0x1U << EXTI_EMR2_EM40_Pos) /*!< 0x00000100 */
#define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk /*!< Event Mask on line 40 */
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0x1FFU << EXTI_EMR2_EM_Pos) /*!< 0x000001FF */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
/****************** Bit definition for EXTI_RTSR2 register ******************/
#define EXTI_RTSR2_RT35_Pos (3U)
@ -19904,7 +19906,8 @@ typedef struct
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5))
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8))
/**************** TIM Instances : external trigger input available ************/
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \

8
CMSIS/STM32L4xx/Include/stm32l4xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx.h
* @author MCD Application Team
* @version V1.3.1
* @date 21-April-2017
* @version V1.3.2
* @date 16-June-2017
* @brief CMSIS STM32L4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -109,11 +109,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V1.3.1
* @brief CMSIS Device version number V1.3.2
*/
#define __STM32L4_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L4_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32L4_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32L4_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32L4_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L4_CMSIS_VERSION ((__STM32L4_CMSIS_VERSION_MAIN << 24)\
|(__STM32L4_CMSIS_VERSION_SUB1 << 16)\

4
CMSIS/STM32L4xx/Include/system_stm32l4xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32l4xx.h
* @author MCD Application Team
* @version V1.3.1
* @date 21-April-2017
* @version V1.3.2
* @date 16-June-2017
* @brief CMSIS Cortex-M4 Device System Source File for STM32L4xx devices.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32_hal_legacy.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief This file contains aliases definition for the STM32Cube HAL constants
* macros and functions maintained for legacy purpose.
******************************************************************************

4
STM32L4xx_HAL_Driver/Inc/stm32_assert_template.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32_assert.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief STM32 assert template file.
* This file should be copied to the application folder and renamed
* to stm32_assert.h.

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief This file contains all the functions prototypes for the HAL
* module driver.
******************************************************************************

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_adc.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of ADC HAL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_adc_ex.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of ADC HAL extended module.
******************************************************************************
* @attention

6
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_can.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_can.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of CAN HAL module.
******************************************************************************
* @attention
@ -258,6 +258,8 @@ typedef struct
#define HAL_CAN_ERROR_BR ((uint32_t)0x00000040) /*!< Bit recessive */
#define HAL_CAN_ERROR_BD ((uint32_t)0x00000080) /*!< LEC dominant */
#define HAL_CAN_ERROR_CRC ((uint32_t)0x00000100) /*!< LEC transfer error */
#define HAL_CAN_ERROR_FOV0 ((uint32_t)0x00000200) /*!< FIFO0 overrun error */
#define HAL_CAN_ERROR_FOV1 ((uint32_t)0x00000400) /*!< FIFO1 overrun error */
/**
* @}
*/

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_comp.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_comp.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of COMP HAL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_conf_template.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_conf.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief HAL configuration template file.
* This file should be copied to the application folder and renamed
* to stm32l4xx_hal_conf.h.

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_cortex.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of CORTEX HAL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_crc.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_crc.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of CRC HAL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_crc_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_crc_ex.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of CRC HAL extended module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cryp.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_cryp.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of CRYP HAL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cryp_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_cryp_ex.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of CRYPEx HAL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dac.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_dac.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of DAC HAL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dac_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_dac_ex.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of DAC HAL Extended module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dcmi.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_dcmi.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of DCMI HAL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_def.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
******************************************************************************

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dfsdm.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_dfsdm.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of DFSDM HAL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_dma.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of DMA HAL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma2d.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_dma2d.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of DMA2D HAL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_firewall.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_firewall.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of FIREWALL HAL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_flash.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of FLASH HAL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_flash_ex.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of FLASH HAL Extended module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_flash_ramfunc.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of FLASH RAMFUNC driver.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_gpio.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of GPIO HAL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_gpio_ex.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of GPIO HAL Extended module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_hash.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_hash.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of HASH HAL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_hash_ex.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_hash_ex.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of HASH HAL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_hcd.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_hcd.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of HCD HAL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_i2c.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of I2C HAL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_i2c_ex.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of I2C HAL Extended module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_irda.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_irda.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of IRDA HAL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_irda_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_irda_ex.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of IRDA HAL Extended module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_iwdg.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_iwdg.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of IWDG HAL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_lcd.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_lcd.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of LCD Controller HAL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_lptim.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_lptim.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of LPTIM HAL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_nand.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_nand.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of NAND HAL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_nor.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_nor.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of NOR HAL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_opamp.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_opamp.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of OPAMP HAL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_opamp_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_opamp_ex.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of OPAMP HAL Extended module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_pcd.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_pcd_ex.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_pwr.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of PWR HAL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_pwr_ex.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of PWR HAL Extended module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_qspi.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_qspi.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of QSPI HAL module.
******************************************************************************
* @attention

46
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_rcc.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of RCC HAL module.
******************************************************************************
* @attention
@ -545,34 +545,34 @@ typedef struct
* @{
*/
/* Flags in the CR register */
#define RCC_FLAG_MSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_MSIRDY))) /*!< MSI Ready flag */
#define RCC_FLAG_HSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSIRDY))) /*!< HSI Ready flag */
#define RCC_FLAG_HSERDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSERDY))) /*!< HSE Ready flag */
#define RCC_FLAG_PLLRDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLRDY))) /*!< PLL Ready flag */
#define RCC_FLAG_PLLSAI1RDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLSAI1RDY))) /*!< PLLSAI1 Ready flag */
#define RCC_FLAG_MSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos)) /*!< MSI Ready flag */
#define RCC_FLAG_HSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< HSI Ready flag */
#define RCC_FLAG_HSERDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< HSE Ready flag */
#define RCC_FLAG_PLLRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)) /*!< PLL Ready flag */
#define RCC_FLAG_PLLSAI1RDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI1RDY_Pos)) /*!< PLLSAI1 Ready flag */
#if defined(RCC_PLLSAI2_SUPPORT)
#define RCC_FLAG_PLLSAI2RDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLSAI2RDY))) /*!< PLLSAI2 Ready flag */
#define RCC_FLAG_PLLSAI2RDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI2RDY_Pos)) /*!< PLLSAI2 Ready flag */
#endif /* RCC_PLLSAI2_SUPPORT */
/* Flags in the BDCR register */
#define RCC_FLAG_LSERDY ((uint32_t)((BDCR_REG_INDEX << 5U) | POSITION_VAL(RCC_BDCR_LSERDY))) /*!< LSE Ready flag */
#define RCC_FLAG_LSECSSD ((uint32_t)((BDCR_REG_INDEX << 5U) | POSITION_VAL(RCC_BDCR_LSECSSD))) /*!< LSE Clock Security System Interrupt flag */
#define RCC_FLAG_LSERDY ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) /*!< LSE Ready flag */
#define RCC_FLAG_LSECSSD ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos)) /*!< LSE Clock Security System Interrupt flag */
/* Flags in the CSR register */
#define RCC_FLAG_LSIRDY ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LSIRDY))) /*!< LSI Ready flag */
#define RCC_FLAG_RMVF ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_RMVF))) /*!< Remove reset flag */
#define RCC_FLAG_FWRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_FWRSTF))) /*!< Firewall reset flag */
#define RCC_FLAG_OBLRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_OBLRSTF))) /*!< Option Byte Loader reset flag */
#define RCC_FLAG_PINRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PINRSTF))) /*!< PIN reset flag */
#define RCC_FLAG_BORRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_BORRSTF))) /*!< BOR reset flag */
#define RCC_FLAG_SFTRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_SFTRSTF))) /*!< Software Reset flag */
#define RCC_FLAG_IWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_IWDGRSTF))) /*!< Independent Watchdog reset flag */
#define RCC_FLAG_WWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_WWDGRSTF))) /*!< Window watchdog reset flag */
#define RCC_FLAG_LPWRRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LPWRRSTF))) /*!< Low-Power reset flag */
#define RCC_FLAG_LSIRDY ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)) /*!< LSI Ready flag */
#define RCC_FLAG_RMVF ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_RMVF_Pos)) /*!< Remove reset flag */
#define RCC_FLAG_FWRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_FWRSTF_Pos)) /*!< Firewall reset flag */
#define RCC_FLAG_OBLRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos)) /*!< Option Byte Loader reset flag */
#define RCC_FLAG_PINRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)) /*!< PIN reset flag */
#define RCC_FLAG_BORRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos)) /*!< BOR reset flag */
#define RCC_FLAG_SFTRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)) /*!< Software Reset flag */
#define RCC_FLAG_IWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)) /*!< Independent Watchdog reset flag */
#define RCC_FLAG_WWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */
#define RCC_FLAG_LPWRRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)) /*!< Low-Power reset flag */
#if defined(RCC_HSI48_SUPPORT)
/* Flags in the CRRCR register */
#define RCC_FLAG_HSI48RDY ((uint32_t)((CRRCR_REG_INDEX << 5U) | POSITION_VAL(RCC_CRRCR_HSI48RDY))) /*!< HSI48 Ready flag */
#define RCC_FLAG_HSI48RDY ((uint32_t)((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos)) /*!< HSI48 Ready flag */
#endif /* RCC_HSI48_SUPPORT */
/**
* @}
@ -3348,7 +3348,7 @@ typedef struct
* @retval None
*/
#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \
MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << POSITION_VAL(RCC_ICSCR_HSITRIM))
MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos)
/**
* @brief Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI)
@ -4055,7 +4055,7 @@ typedef struct
#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)( RCC_ICSCR_HSITRIM >> POSITION_VAL(RCC_ICSCR_HSITRIM)))
#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)( RCC_ICSCR_HSITRIM >> RCC_ICSCR_HSITRIM_Pos))
#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))

48
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_rcc_ex.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of RCC HAL Extended module.
******************************************************************************
* @attention
@ -772,18 +772,18 @@ typedef struct
#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
#define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \
WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) | \
((((__PLLSAI1Q__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q)) | \
((((__PLLSAI1R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R)) | \
((__PLLSAI1P__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV)))
WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \
((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \
((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \
((__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos))
#else
#define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \
WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) | \
(((__PLLSAI1P__) >> 4U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P)) | \
((((__PLLSAI1Q__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q)) | \
((((__PLLSAI1R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R)))
WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \
(((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) | \
((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \
((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos))
#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
@ -803,7 +803,7 @@ typedef struct
* @retval None
*/
#define __HAL_RCC_PLLSAI1_MULN_CONFIG(__PLLSAI1N__) \
MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N))
MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)
/** @brief Macro to configure the PLLSAI1 clock division factor P.
*
@ -821,12 +821,12 @@ typedef struct
#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
#define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \
MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV, (__PLLSAI1P__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV))
MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV, (__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)
#else
#define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \
MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P, ((__PLLSAI1P__) >> 4U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P))
MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P, ((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos)
#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
@ -843,7 +843,7 @@ typedef struct
* @retval None
*/
#define __HAL_RCC_PLLSAI1_DIVQ_CONFIG(__PLLSAI1Q__) \
MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q))
MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos)
/** @brief Macro to configure the PLLSAI1 clock division factor R.
*
@ -858,7 +858,7 @@ typedef struct
* @retval None
*/
#define __HAL_RCC_PLLSAI1_DIVR_CONFIG(__PLLSAI1R__) \
MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R))
MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)
/**
* @brief Macros to enable or disable the PLLSAI1.
@ -929,16 +929,16 @@ typedef struct
#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \
WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)) | \
((((__PLLSAI2R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R)) | \
((__PLLSAI2P__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2PDIV)))
WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \
((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \
((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos))
#else
#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \
WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)) | \
(((__PLLSAI2P__) >> 4U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P)) | \
((((__PLLSAI2R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R)))
WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \
(((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) | \
((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos))
#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
@ -959,7 +959,7 @@ typedef struct
* @retval None
*/
#define __HAL_RCC_PLLSAI2_MULN_CONFIG(__PLLSAI2N__) \
MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N, (__PLLSAI2N__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N))
MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N, (__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos)
/** @brief Macro to configure the PLLSAI2 clock division factor P.
*
@ -974,7 +974,7 @@ typedef struct
* @retval None
*/
#define __HAL_RCC_PLLSAI2_DIVP_CONFIG(__PLLSAI2P__) \
MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P, ((__PLLSAI2P__) >> 4U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P))
MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P, ((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos)
/** @brief Macro to configure the PLLSAI2 clock division factor R.
*
@ -989,7 +989,7 @@ typedef struct
* @retval None
*/
#define __HAL_RCC_PLLSAI2_DIVR_CONFIG(__PLLSAI2R__) \
MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R, (((__PLLSAI2R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R))
MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R, (((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos)
/**
* @brief Macros to enable or disable the PLLSAI2.

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rng.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_rng.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of RNG HAL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_rtc.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of RTC HAL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc_ex.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_rtc_ex.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of RTC HAL Extended module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sai.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_sai.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of SAI HAL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sd.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_sd.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of SD HAL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smartcard.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_smartcard.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of SMARTCARD HAL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smartcard_ex.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_smartcard_ex.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of SMARTCARD HAL Extended module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smbus.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_smbus.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of SMBUS HAL module.
******************************************************************************
* @attention

6
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_spi.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of SPI HAL module.
******************************************************************************
* @attention
@ -611,6 +611,8 @@ typedef struct __SPI_HandleTypeDef
#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1U) && ((POLYNOMIAL) <= 0xFFFFU) && (((POLYNOMIAL)&0x1U) != 0U))
#define IS_SPI_DMA_HANDLE(HANDLE) ((HANDLE) != NULL)
/**
* @}

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_spi_ex.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of SPI HAL Extended module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sram.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_sram.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of SRAM HAL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_swpmi.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_swpmi.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of SWPMI HAL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_tim.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of TIM HAL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_tim_ex.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of TIM HAL Extended module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tsc.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_tsc.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of TSC HAL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_uart.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of UART HAL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_uart_ex.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of UART HAL Extended module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_usart.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_usart.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of USART HAL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_usart_ex.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_usart_ex.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of USART HAL Extended module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_wwdg.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_wwdg.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of WWDG HAL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_adc.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of ADC LL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_bus.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_bus.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of BUS LL module.
@verbatim

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_comp.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_comp.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of COMP LL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_cortex.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_cortex.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of CORTEX LL module.
@verbatim
==============================================================================

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crc.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_crc.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of CRC LL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crs.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_crs.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of CRS LL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dac.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_dac.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of DAC LL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dma.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_dma.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of DMA LL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dma2d.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_dma2d.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of DMA2D LL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_exti.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_exti.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of EXTI LL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_fmc.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_fmc.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of FMC HAL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_gpio.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_gpio.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of GPIO LL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_i2c.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_i2c.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of I2C LL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_iwdg.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_iwdg.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of IWDG LL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_lptim.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_lptim.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of LPTIM LL module.
******************************************************************************
* @attention

4
STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_lpuart.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_lpuart.h
* @author MCD Application Team
* @version V1.7.1
* @date 21-April-2017
* @version V1.7.2
* @date 16-June-2017
* @brief Header file of LPUART LL module.
******************************************************************************
* @attention

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