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F4_HAL/rcc: Adjust computation of SYSCLK to retain precision.

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Damien George 2017-08-27 21:55:04 +10:00 committed by Damien George
parent e7710b396e
commit 009dd8778d
1 changed files with 6 additions and 1 deletions
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7
STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c
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@ -891,7 +891,12 @@ __weak uint32_t HAL_RCC_GetSysClockFreq(void)
if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
{
/* HSE used as PLL clock source */
pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
//pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
// dpgeorge: Adjust the way the arithmetic is done so it retains
// precision for the case that pllm doesn't evenly divide HSE_VALUE.
// Must be sure not to overflow, so divide by 4 first. HSE_VALUE
// should be a multiple of 4 (being a multiple of 100 is enough).
pllvco = ((HSE_VALUE / 4) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))) / pllm * 4;
}
else
{