Angus Gratton 068d9bf2cf rp2: Fix USB PLL glitch during wake from light sleep. ... Follow-up to a84c7a0ed9, this commit works most of the time but has an intermittent bug where USB doesn't resume as expected after waking from light sleep. Turns out waking calls clocks_init() which will re-initialise the USB PLL. Most of the time this is OK but occasionally it seems like the clock glitches the USB peripheral and it stops working until the next hard reset. Adds a machine.lightsleep() test that consistently hangs in the first two dozen iterations on rp2 without this fix. Passed over 100 times in a row with this fix. The test is currently rp2-only as it seems similar lightsleep USB issues exist on other ports (both pyboard and ESP32-S3 native USB don't send any data to the host after waking, until they receive something from the host first.) This work was funded through GitHub Sponsors. Signed-off-by: Angus Gratton <angus@redyak.com.au>		2024-06-25 16:25:19 +10:00
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cc3200	all: Prune trailing whitespace.	2024-03-07 16:25:17 +11:00
esp32	tests: Move port-specific test directories into tests/ports/ directory.	2024-01-22 11:48:27 +11:00
qemu-arm	tests: Move port-specific test directories into tests/ports/ directory.	2024-01-22 11:48:27 +11:00
renesas-ra	tests: Move port-specific test directories into tests/ports/ directory.	2024-01-22 11:48:27 +11:00
rp2	rp2: Fix USB PLL glitch during wake from light sleep.	2024-06-25 16:25:19 +10:00
stm32	tests: Move port-specific test directories into tests/ports/ directory.	2024-01-22 11:48:27 +11:00
stm32_hardware	stm32/dma: Add D-cache protection for DMA RX operations, including SPI.	2024-03-08 12:19:48 +11:00
unix	tests/ports/unix: Add coverage test for frozen functions and generators.	2024-02-16 14:17:01 +11:00
webassembly	webassembly/api: Allow specifying the pystack size.	2024-06-20 00:26:08 +10:00