9dcad25de6
This commit introduces support for writing inline assembler code snippets when targeting Xtensa cores that use register windows (eg. the whole ESP32 family). Opcodes support is still limited to what the ESP8266 supports (as in, LX3 cores opcodes), however each LX core version is guaranteed to support all previous versions' opcodes as well. The ESP32 does not have the inline assembler enabled by default, following the existing expectations when it comes to firmware footprint. Since now emitted functions may have one of two possible exit sequences, the L32I test had to be fixed. It would return the word containing the L32I opcode itself, but the upper 8 bits of the word came from the following opcode - which can change depending on the exit code sequence. Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
10 lines
155 B
Plaintext
10 lines
155 B
Plaintext
0x4030201
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0xf0002022
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0x22
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200
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-200
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array('B', [17, 255, 51, 68])
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array('h', [100, -123, -100, -200])
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array('i', [100000, -123456, 300000, -400000])
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300000
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