204 lines
6.9 KiB
C
204 lines
6.9 KiB
C
/*
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* (c) Copyright 2018 by Coinkite Inc. This file is covered by license found in COPYING-CC.
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*/
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/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2013, 2014 Damien P. George
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "basics.h"
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#include "clocks.h"
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#include "stm32l4xx_hal.h"
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// HSE is used and is 8MHz
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// - doing a complete setup here, and not changing in MicroPython anymore
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// - this chip is well made and can handle later changes to clocks
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// - lots of internal RC osc we can use as well... HSI, MSI and HSI48
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#if HCLK_FREQUENCY == 80000000
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// To get 80Mhz for SYSCLK...
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// 8Mhz (HSE) => /2 (M) *40 (N) /2 (R) => 80Mhz
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# define CKCC_CLK_PLLM (2)
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# define CKCC_CLK_PLLN (40)
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# define CKCC_CLK_PLLR (2)
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# define CKCC_CLK_PLLP (7)
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# define CKCC_CLK_PLLQ (4)
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#endif
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#if HCLK_FREQUENCY == 120000000
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// For for 120Mhz SYSCLK...
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// 8Mhz (HSE) => /2 (M) *60 (N) /2 (R) => 120Mhz
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// R output => main sysclk (target 120)
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// Q output => should be 48Mhz for RNG and OCTOSPI maybe
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# define CKCC_CLK_PLLM (2)
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# define CKCC_CLK_PLLN (60)
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# define CKCC_CLK_PLLR (2)
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# define CKCC_CLK_PLLP (7)
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# define CKCC_CLK_PLLQ (5)
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#endif
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// systick_setup()
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//
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void
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systick_setup(void)
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{
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const uint32_t ticks = HCLK_FREQUENCY/1000;
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SysTick->LOAD = (ticks - 1);
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SysTick->VAL = 0;
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SysTick->CTRL = SYSTICK_CLKSOURCE_HCLK | SysTick_CTRL_ENABLE_Msk;
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}
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// from HAL/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c
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//
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void
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system_init0(void)
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{
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#if defined(USER_VECT_TAB_ADDRESS)
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/* Configure the Vector Table location -------------------------------------*/
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SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
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#endif
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/* FPU settings ------------------------------------------------------------*/
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
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#endif
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/* Reset the RCC clock configuration to the default reset state ------------*/
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/* Set MSION bit */
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RCC->CR |= RCC_CR_MSION;
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/* Reset CFGR register */
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RCC->CFGR = 0x00000000U;
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/* Reset HSEON, CSSON , HSION, and PLLON bits */
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RCC->CR &= 0xEAF6FFFFU;
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/* Reset PLLCFGR register */
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RCC->PLLCFGR = 0x00001000U;
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/* Reset HSEBYP bit */
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RCC->CR &= 0xFFFBFFFFU;
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/* Disable all interrupts */
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RCC->CIER = 0x00000000U;
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}
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// clocks_setup()
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//
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void
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clocks_setup(void)
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{
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RCC_ClkInitTypeDef RCC_ClkInitStruct;
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RCC_OscInitTypeDef RCC_OscInitStruct;
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// setup power supplies
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HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST);
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// Configure LSE Drive Capability
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__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
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// Enable HSE Oscillator and activate PLL with HSE as source
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
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RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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RCC_OscInitStruct.LSEState = RCC_LSE_OFF;
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RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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// Select PLL as system clock source and configure
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// the HCLK, PCLK1 and PCLK2 clocks dividers
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RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK
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| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_OscInitStruct.PLL.PLLM = CKCC_CLK_PLLM;
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RCC_OscInitStruct.PLL.PLLN = CKCC_CLK_PLLN;
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RCC_OscInitStruct.PLL.PLLP = CKCC_CLK_PLLP;
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RCC_OscInitStruct.PLL.PLLQ = CKCC_CLK_PLLQ;
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RCC_OscInitStruct.PLL.PLLR = CKCC_CLK_PLLR;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
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HAL_RCC_OscConfig(&RCC_OscInitStruct);
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HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
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// DIS-able MSI-Hardware auto calibration mode with LSE
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CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN);
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RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
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PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SAI1|RCC_PERIPHCLK_I2C2
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|RCC_PERIPHCLK_USB |RCC_PERIPHCLK_ADC
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|RCC_PERIPHCLK_RNG |RCC_PERIPHCLK_RTC;
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PeriphClkInitStruct.I2c2ClockSelection = RCC_I2C2CLKSOURCE_PCLK1;
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// PLLSAI is used to clock USB, ADC, I2C1 and RNG. The frequency is
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// HSE(8MHz)/PLLM(2)*PLLSAI1N(24)/PLLSAIQ(2) = 48MHz.
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//
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PeriphClkInitStruct.Sai1ClockSelection = RCC_SAI1CLKSOURCE_PLLSAI1;
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PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLLSAI1;
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PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
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PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_HSE_DIV32; // but unused
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PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_PLLSAI1;
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PeriphClkInitStruct.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE;
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PeriphClkInitStruct.PLLSAI1.PLLSAI1M = 2;
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PeriphClkInitStruct.PLLSAI1.PLLSAI1N = 24;
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PeriphClkInitStruct.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
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PeriphClkInitStruct.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
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PeriphClkInitStruct.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
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PeriphClkInitStruct.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_SAI1CLK
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|RCC_PLLSAI1_48M2CLK
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|RCC_PLLSAI1_ADC1CLK;
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HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
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__HAL_RCC_RTC_ENABLE();
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__HAL_RCC_HASH_CLK_ENABLE(); // for SHA256
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__HAL_RCC_SPI1_CLK_ENABLE(); // for OLED
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//__HAL_RCC_SPI2_CLK_ENABLE(); // for SPI flash
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__HAL_RCC_DMAMUX1_CLK_ENABLE(); // (need this) because code missing in mpy?
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// for SE2
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__HAL_RCC_I2C2_CLK_ENABLE();
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__HAL_RCC_I2C2_FORCE_RESET();
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__HAL_RCC_I2C2_RELEASE_RESET();
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// setup SYSTICK, but we don't have the irq hooked up and not using HAL
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// but we use it in polling mode for delay_ms()
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systick_setup();
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}
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// EOF
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