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makes binary

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This commit is contained in:
Peter D. Gray 2023-07-14 09:18:06 -04:00 committed by scgbckbone
parent 3c71a30cbb
commit dd2be687e1
20 changed files with 2325 additions and 0 deletions
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6
.gitmodules vendored
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[submodule "stm32/mk4-bootloader/hal"] [submodule "stm32/mk4-bootloader/hal"]
path = stm32/mk4-bootloader/hal path = stm32/mk4-bootloader/hal
url = https://github.com/STMicroelectronics/STM32CubeL4.git url = https://github.com/STMicroelectronics/STM32CubeL4.git
[submodule "misc/gpu/external/stm32c0xx_hal_driver"]
path = misc/gpu/external/stm32c0xx_hal_driver
url = https://github.com/STMicroelectronics/stm32c0xx_hal_driver.git
[submodule "misc/gpu/external/cmsis_device_c0"]
path = misc/gpu/external/cmsis_device_c0
url = https://github.com/STMicroelectronics/cmsis_device_c0.git

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misc/gpu/.gitignore vendored Normal file
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gpu.lss
gpu.sym
gpu.bin.tmp

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misc/gpu/Makefile Normal file
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# (c) Copyright 2023 by Coinkite Inc. This file is covered by license found in COPYING-CC.
#
# Makefile for Q1's GPU co-processor.
#
# Targets:
# all - make everything, look for dafu.elf inparticular
# clean - delete intermediates
# clobber - delete all build products
#
# Toolchain
TOOLCHAIN = arm-none-eabi-
CC = $(TOOLCHAIN)gcc
OBJDUMP = $(TOOLCHAIN)objdump
OBJCOPY = $(TOOLCHAIN)objcopy
NM = $(TOOLCHAIN)nm
SIZE = $(TOOLCHAIN)size
# Basename of all targets
TARGET_NAME = gpu
# Source files, listed here as the object files they will become.
OBJS += startup.o
OBJS += main.o version.o
OBJS += stm32c0xx_hal.o system_stm32c0xx.o interrupts.o
# Have to have copies of these because the DMA and interrupt stuff
# needs to be commented-out.
#OBJS += stm32l4xx_hal_gpio.o stm32l4xx_hal_spi.o
#OBJS += stm32l4xx_hal_rcc.o stm32l4xx_hal_rcc_ex.o
# Where we will end up in the memory map (at start of flash)
GPU_FLASH_BASE = 0x08000000
GPU_FLASH_SIZE = 0x4000
GPU_FLASH_LAST = 0x08004000
# Use all of 6k of SRAM...
GPU_SRAM_BASE = 0x20000000
GPU_SRAM_SIZE = 0x00001800
# Compiler flags.
CFLAGS = -I. -Wall --std=gnu99 -Os -g3 \
-mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=soft -mtune=cortex-m0 \
-ffunction-sections -fdata-sections \
-mcpu=cortex-m0 -DMCU_SERIES_C0 -DSTM32C011xx
#-DUSE_HAL_DRIVER
# Pass in the locations of stuff
CFLAGS += -D GPU_FLASH_BASE=$(GPU_FLASH_BASE) -D GPU_FLASH_SIZE=$(GPU_FLASH_SIZE)
CFLAGS += -D GPU_SRAM_BASE=$(GPU_SRAM_BASE) -D GPU_SRAM_SIZE=$(GPU_SRAM_SIZE)
# Header file search path
INC_PATHS = external/cmsis_device_c0/Include \
external/stm32c0xx_hal_driver/Inc \
../../external/micropython/lib/cmsis/inc
CFLAGS += $(foreach INC,$(INC_PATHS),-I$(INC))
# Specialized linker-script here. Not the standard one!
#
LINKER_SCRIPT = link-script.ld
LDFLAGS += -Wl,-T$(LINKER_SCRIPT)
#LDFLAGS += -flto -Wl,--gc-sections --specs=nano.specs
LDFLAGS += -fpic -Wl,--gc-sections --specs=nano.specs
LDFLAGS += -Wl,--defsym,GPU_FLASH_BASE=$(GPU_FLASH_BASE)
LDFLAGS += -Wl,--defsym,GPU_FLASH_SIZE=$(GPU_FLASH_SIZE)
LDFLAGS += -Wl,--defsym,GPU_SRAM_BASE=$(GPU_SRAM_BASE)
LDFLAGS += -Wl,--defsym,GPU_SRAM_SIZE=$(GPU_SRAM_SIZE)
LDFLAGS += -Wl,-Map=$(TARGET_NAME).map
ASFLAGS += -Wa,--defsym,GPU_FLASH_BASE=$(GPU_FLASH_BASE) -Wa,--defsym,GPU_FLASH_SIZE=$(GPU_FLASH_SIZE)
ASFLAGS += -Wa,--defsym,GPU_SRAM_BASE=$(GPU_SRAM_BASE) -Wa,--defsym,GPU_SRAM_SIZE=$(GPU_SRAM_SIZE)
TARGET_ELF = $(TARGET_NAME).elf
TARGETS = $(TARGET_NAME).lss $(TARGET_NAME).bin $(TARGET_NAME).sym
all: $(TARGETS)
# recompile on any Makefile change, because with a small project like this...
$(OBJS): Makefile
$(TARGETS): $(TARGET_ELF) Makefile
# link step
$(TARGET_ELF): $(OBJS) $(LINKER_SCRIPT) Makefile
$(CC) $(CFLAGS) -o $(TARGET_ELF) $(LDFLAGS) $(OBJS)
$(SIZE) -Ax $@
# detailed listing, very handy
%.lss: $(TARGET_ELF)
$(OBJDUMP) -h -S $< > $@
# symbol dump, meh
%.sym: $(TARGET_ELF)
$(NM) -n $< > $@
# raw binary, forced to right size, pad w/ 0xff
%.bin: $(TARGET_ELF)
$(OBJCOPY) -O binary --pad-to $(GPU_FLASH_LAST) --gap-fill 0xff $< $@.tmp
dd bs=$(shell printf "%d" $(GPU_FLASH_SIZE)) count=1 if=$@.tmp of=$@
# assumes openocd running from current directory
up:
echo 'flash write_image $(TARGET_ELF)' | nc localhost 4444
# make a 'release' build
release: code-committed clean all capture
release: CFLAGS += -DRELEASE=1 -Werror
.PHONY: code-committed
code-committed:
@echo ""
@echo "Are all changes commited already?"
git diff --stat --exit-code .
@echo '... yes'
# these files are what we capture and store for each release.
DELIVERABLES = $(TARGET_NAME).bin $(TARGET_NAME).lss
checksums.txt: $(DELIVERABLES)
shasum -a 256 $(DELIVERABLES) > $@
# Track released versions
.PHONY: capture
capture: version.txt version-full.txt $(DELIVERABLES) checksums.txt
V=`cat version.txt` && cat checksums.txt > releases/$$V.txt && cat version-full.txt >> releases/$$V.txt && mkdir -p releases/$$V; cp $(DELIVERABLES) releases/$$V
@echo
@echo " Version: " `cat version.txt`
@echo
V=`cat version.txt` && git tag -am "Mk4 Bootloader version $$V" "mk4-bootloader-"$$V
git add -f releases/*/bootloader.* releases/*.txt
# Pull out the version string from binary object (already linked in) and
# construct a text file (version.txt) with those contents
version.txt version-full.txt: version.o Makefile
$(OBJCOPY) -O binary -j .rodata.version_string version.o version-tmp.txt
cat version-tmp.txt | sed -e 's/ .*//' | sed -e 's/ .*//' > version.txt
cat version-tmp.txt | tr '\0' '\n' > version-full.txt
@echo
@echo "Version string: " `cat version-full.txt`
@echo
$(RM) version-tmp.txt
# nice version numbers.
BUILD_TIME = $(shell date '+%Y%m%d.%H%M%S')
BRANCH = $(shell git rev-parse --abbrev-ref HEAD)
SHA_VERSION = $(shell git rev-parse --short HEAD)
GIT_HASH = "$(BRANCH)@$(SHA_VERSION)"
version.o: CFLAGS += -DBUILD_TIME='"$(BUILD_TIME)"' -DGIT_HASH='$(GIT_HASH)'
version.o: Makefile version.h
clean:
$(RM) $(OBJS)
clobber: clean
$(RM) $(TARGETS)
debug:
arm-none-eabi-gdb bootloader.elf -x gogo.gdb
xxx:
@echo CFLAGS = $(CFLAGS)
@echo
@echo OBJS = $(OBJS)
tags:
ctags -f .tags *.[ch] -R $(INC_PATHS)
# EOF

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# GPU on Q1
The name is a joke. It's not a GPU, just a very simple and cheap micro that can
animate a progress bar. And that's all we want it to do.
It is field upgradable, but we may remove that and start locking it down in
production once it's features are stable.
## Hardware
It's a STM32C011F4:
- 16k bytes of Flash
- 6k bytes of RAM
- 4-48Mhz
- 18 GPIO
- 20 pins
Of the two TagConnect spots, the GPU is the inboard one; other is for main micro.
## Notes
- AN4221 describes the protocol used to load the flash
- timing is sensitive, but more important is where the i2c start/stops fall:
```python
>>> from machine import I2C, Pin
>>> i2c = I2C(1, freq=400000)
>>> r = Pin('G_RESET')
>>> r
Pin(Pin.cpu.E6, mode=Pin.OUT)
>>> r.init(mode=Pin.OPEN_DRAIN, pull=Pin.PULL_UP)
>>> r()
0
>>> r(1)
>>> r()
1
>>> [hex(i) for i in i2c.scan()]
['0x2d', '0x51', '0x53', '0x55', '0x57', '0x64']
# for SWI to work, also:
>>> gg=Pin('G_SWCLK_B0')
>>> gg.init(mode=Pin.IN)
# Get - reveals bootloader version, commands (v1.2)
>>> i2c.writeto(0x64, b'\x00\xff'); i2c.readfrom(0x64, 1); i2c.readfrom(0x64, 20); i2c.readfrom(0x64, 1);
2
b'y'
b'\x12\x11\x00\x01\x02\x11!1Dcs\x82\x922Edt\x83\x93\xa1'
b'y'
# Get ID command
>>> i2c.writeto(0x64, b'\x02\xfd'); i2c.readfrom(0x64, 1); [hex(i) for i in i2c.readfrom(0x64, 3)]; i2c.readfrom(2x64, 1);
b'y'
['0x1', '0x4', '0x43']
b'y'
```

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misc/gpu/external/cmsis_device_c0 vendored Submodule

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Subproject commit 7e32bf9d8117ee4c8f6a1d138b814fc24bf4c906

1
misc/gpu/external/stm32c0xx_hal_driver vendored Submodule

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Subproject commit 4c5e3e45a8478a33decb1f45d663f485f89c459b

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// from https://github.com/STMicroelectronics/STM32CubeC0/blob/main/Projects/STM32C0116-DK/Templates_LL/Src/stm32c0xx_it.c
/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32c0xx_it.c
* @brief Interrupt Service Routines.
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
#include "interrupts.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN TD */
/* USER CODE END TD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */
/* USER CODE END PD */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN PV */
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/* External variables --------------------------------------------------------*/
/* USER CODE BEGIN EV */
/* USER CODE END EV */
/******************************************************************************/
/* Cortex Processor Interruption and Exception Handlers */
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
{
}
/* USER CODE END NonMaskableInt_IRQn 1 */
}
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_HardFault_IRQn 0 */
/* USER CODE END W1_HardFault_IRQn 0 */
}
}
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
/* USER CODE BEGIN SVC_IRQn 0 */
/* USER CODE END SVC_IRQn 0 */
/* USER CODE BEGIN SVC_IRQn 1 */
/* USER CODE END SVC_IRQn 1 */
}
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
/* USER CODE BEGIN PendSV_IRQn 0 */
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
/******************************************************************************/
/* STM32C0xx Peripheral Interrupt Handlers */
/* Add here the Interrupt Handlers for the used peripherals. */
/* For the available peripheral interrupt handler names, */
/* please refer to the startup file (startup_stm32c0xx.s). */
/******************************************************************************/
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */

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#pragma once
void NMI_Handler(void);
void HardFault_Handler(void);
void SVC_Handler(void);
void PendSV_Handler(void);
void SysTick_Handler(void);

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/**
*
* a specialized linker script:
* - limits itself to just part of the device
* - assumes only a small amount of ram is available.
* - reference: <https://sourceware.org/binutils/docs/ld/>
* - spaces actually matter in expressions in this file
*
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
/* Memory Spaces Definitions */
MEMORY
{
FLASH (rx) : ORIGIN = GPU_FLASH_BASE, LENGTH = GPU_FLASH_SIZE
RAM (rwx) : ORIGIN = GPU_SRAM_BASE, LENGTH = GPU_SRAM_SIZE
}
/* from /Applications/ARM/share/gcc-arm-none-eabi/samples/ldscripts/gcc.ld */
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __copy_table_start__
* __copy_table_end__
* __zero_table_start__
* __zero_table_end__
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)
SECTIONS
{
.text :
{
KEEP(*(.isr_vector))
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
/* To copy multiple ROM to RAM sections,
* uncomment .copy.table section and,
* define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
/*
.copy.table :
{
. = ALIGN(4);
__copy_table_start__ = .;
LONG (__etext)
LONG (__data_start__)
LONG (__data_end__ - __data_start__)
LONG (__etext2)
LONG (__data2_start__)
LONG (__data2_end__ - __data2_start__)
__copy_table_end__ = .;
} > FLASH
*/
/* To clear multiple BSS sections,
* uncomment .zero.table section and,
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
/*
.zero.table :
{
. = ALIGN(4);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
LONG (__bss2_start__)
LONG (__bss2_end__ - __bss2_start__)
__zero_table_end__ = .;
} > FLASH
*/
/* Location counter can end up 2byte aligned with narrow Thumb code but
__etext is assumed by startup code to be the LMA of a section in RAM
which must be 4byte aligned */
__etext = ALIGN (4);
.data : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM
.bss :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > RAM
.heap (COPY):
{
__end__ = .;
PROVIDE(end = .);
*(.heap*)
__HeapLimit = .;
} > RAM
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (COPY):
{
*(.stack*)
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
/* my values for startup.S code inhirited */
PROVIDE(_estack = __StackTop);
PROVIDE(_sidata = __init_array_start); /* start address for the init values of the .data section. */
PROVIDE(_sdata = __data_start__); /* start address for the .data section. */
PROVIDE(_edata = __data_end__); /* end address for the .data section. */
PROVIDE(_sbss = __bss_start__); /* start address for the .bss section. */
PROVIDE(_ebss = __bss_end__); /* end address for the .bss section. */
}

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#include "main.h"
int main(void)
{
// from https://github.com/STMicroelectronics/STM32CubeC0/blob/main/Projects/STM32C0316-DK/Examples_LL/GPIO/GPIO_InfiniteLedToggling_Init/Src/main.c
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SYSCFG);
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
SystemCoreClockUpdate();
while(1) ;
return 0;
}
void exit(int unused)
{
while(1) ;
}

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#include "stm32c0xx.h"
#include "stm32c0xx_ll_bus.h"

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# This script configures OpenOCD for use with an ST-Link V2 programmer/debugger
# and an STM32L4S5 target microcontroller.
#
# To flash your firmware:
#
# $ openocd -f openocd_stm32l4x6.cfg \
# -c "stm_flash build-BOARD/firmware0.bin 0x08000000 build-BOARD/firmware1.bin 0x08004000"
#
# For a gdb server on port 3333:
#
# $ openocd -f openocd_stm32l4x6.cfg
source [find interface/stlink.cfg]
transport select hla_swd
#source [find target/stm32c011.cfg]
source stm32c0x.cfg
# from <http://www.openstm32.org/forumthread7123>
#reset_config srst_only
reset_config none separate
init
proc stm_flash { BIN0 ADDR0 BIN1 ADDR1 } {
reset halt
sleep 100
wait_halt 2
flash write_image erase $BIN0 $ADDR0
sleep 100
verify_image $BIN0 $ADDR0
sleep 100
flash write_image erase $BIN1 $ADDR1
sleep 100
verify_image $BIN1 $ADDR1
sleep 100
reset run
shutdown
}
proc stm_erase {} {
reset halt
sleep 100
stm32l4x mass_erase 0
sleep 100
shutdown
}
proc dfu {} {
# reset and get it started; doesn't work from "reset halt" nor "reset init"
reset run
halt
# SYSCFG->MEMRMP setup for system flash @ 0x0
# do __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH()
mww 0x40010000 0x1
# do "mdw 0x0 2" to learn these two values
reg msp 0x20003560
reg pc 0x1fff51db
resume
sleep 500
}

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/*
* (c) Copyright 2023 by Coinkite Inc. This file is covered by license found in COPYING-CC.
*/
/**
******************************************************************************
* @file startup_stm32c011xx.s
* @author MCD Application Team
* @brief STM32C011xx devices vector table GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M0+ processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
*******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
*******************************************************************************
*/
.syntax unified
.cpu cortex-m0plus
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M0. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word 0
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler /* Window WatchDog */
.word 0 /* reserved */
.word RTC_IRQHandler /* RTC through the EXTI line */
.word FLASH_IRQHandler /* FLASH */
.word RCC_IRQHandler /* RCC */
.word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */
.word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */
.word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */
.word 0 /* reserved */
.word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
.word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */
.word DMAMUX1_IRQHandler /* DMAMUX1 */
.word ADC1_IRQHandler /* ADC1 */
.word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.word 0 /* reserved */
.word TIM3_IRQHandler /* TIM3 */
.word 0 /* reserved */
.word 0 /* reserved */
.word TIM14_IRQHandler /* TIM14 */
.word 0 /* reserved */
.word TIM16_IRQHandler /* TIM16 */
.word TIM17_IRQHandler /* TIM17 */
.word I2C1_IRQHandler /* I2C1 */
.word 0 /* reserved */
.word SPI1_IRQHandler /* SPI1 */
.word 0 /* reserved */
.word USART1_IRQHandler /* USART1 */
.word USART2_IRQHandler /* USART2 */
.word 0 /* reserved */
.word 0 /* reserved */
.word 0 /* reserved */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak RTC_IRQHandler
.thumb_set RTC_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_1_IRQHandler
.thumb_set EXTI0_1_IRQHandler,Default_Handler
.weak EXTI2_3_IRQHandler
.thumb_set EXTI2_3_IRQHandler,Default_Handler
.weak EXTI4_15_IRQHandler
.thumb_set EXTI4_15_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_3_IRQHandler
.thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
.weak DMAMUX1_IRQHandler
.thumb_set DMAMUX1_IRQHandler,Default_Handler
.weak ADC1_IRQHandler
.thumb_set ADC1_IRQHandler,Default_Handler
.weak TIM1_BRK_UP_TRG_COM_IRQHandler
.thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM14_IRQHandler
.thumb_set TIM14_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak I2C1_IRQHandler
.thumb_set I2C1_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler

74
misc/gpu/stm32c0x.cfg Normal file
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# SPDX-License-Identifier: GPL-2.0-or-later
# script for stm32c0x family
#
# stm32c0 devices support SWD transports only.
#
source [find target/swj-dp.tcl]
source [find mem_helper.tcl]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME stm32c0x
}
set _ENDIAN little
# Work-area is a space in RAM used for flash programming
# By default use 6kB
if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE
} else {
set _WORKAREASIZE 0x1800
}
#jtag scan chain
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
# SWD IDCODE (single drop, arm)
set _CPUTAPID 0x0bc11477
}
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME
flash bank $_CHIPNAME.otp stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME
# reasonable default
adapter speed 2000
adapter srst delay 100
if {[using_jtag]} {
jtag_ntrst_delay 100
}
reset_config srst_nogate
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
}
$_TARGETNAME configure -event examine-end {
# Enable DBGMCU clock
# RCC_APB1ENR |= DBGMCUEN
mmw 0x4002103C 0x08000000 0
# Enable debug during low power modes (uses more power)
# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
mmw 0x40015804 0x00000006 0
# Stop watchdog counters during halt
# DBGMCU_APB1_FZ |= DBG_WDGLS_STOP | DBG_WWDG_STOP
mmw 0x40015808 0x00001800 0
}

636
misc/gpu/stm32c0xx_hal.c Normal file
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/**
******************************************************************************
* @file stm32c0xx_hal.c
* @author MCD Application Team
* @brief HAL module driver.
* This is the common part of the HAL initialization
*
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The common HAL driver contains a set of generic and common APIs that can be
used by the PPP peripheral drivers and the user to start using the HAL.
[..]
The HAL contains two APIs' categories:
(+) Common HAL APIs
(+) Services HAL APIs
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32c0xx_hal.h"
/** @addtogroup STM32C0xx_HAL_Driver
* @{
*/
/** @addtogroup HAL
* @brief HAL module driver
* @{
*/
#ifdef HAL_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup HAL_Private_Constants HAL Private Constants
* @{
*/
/**
* @brief STM32C0xx HAL Driver version number
*/
#define __STM32C0xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32C0xx_HAL_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */
#define __STM32C0xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32C0xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32C0xx_HAL_VERSION ((__STM32C0xx_HAL_VERSION_MAIN << 24U)\
|(__STM32C0xx_HAL_VERSION_SUB1 << 16U)\
|(__STM32C0xx_HAL_VERSION_SUB2 << 8U )\
|(__STM32C0xx_HAL_VERSION_RC))
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Exported variables ---------------------------------------------------------*/
/** @defgroup HAL_Exported_Variables HAL Exported Variables
* @{
*/
__IO uint32_t uwTick;
uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup HAL_Exported_Functions
* @{
*/
/** @addtogroup HAL_Exported_Functions_Group1
* @brief HAL Initialization and Configuration functions
*
@verbatim
===============================================================================
##### HAL Initialization and Configuration functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize the Flash interface the NVIC allocation and initial time base
clock configuration.
(+) De-initialize common part of the HAL.
(+) Configure the time base source to have 1ms time base with a dedicated
Tick interrupt priority.
(++) SysTick timer is used by default as source of time base, but user
can eventually implement his proper time base source (a general purpose
timer for example or other time source), keeping in mind that Time base
duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
handled in milliseconds basis.
(++) Time base configuration function (HAL_InitTick ()) is called automatically
at the beginning of the program after reset by HAL_Init() or at any time
when clock is configured, by HAL_RCC_ClockConfig().
(++) Source of time base is configured to generate interrupts at regular
time intervals. Care must be taken if HAL_Delay() is called from a
peripheral ISR process, the Tick interrupt line must have higher priority
(numerically lower) than the peripheral interrupt. Otherwise the caller
ISR process will be blocked.
(++) functions affecting time base configurations are declared as __weak
to make override possible in case of other implementations in user file.
@endverbatim
* @{
*/
/**
* @brief Configure the Flash prefetch and the Instruction cache,
* the time base source, NVIC and any required global low level hardware
* by calling the HAL_MspInit() callback function to be optionally defined in user file
* stm32c0xx_hal_msp.c.
*
* @note HAL_Init() function is called at the beginning of program after reset and before
* the clock configuration.
*
* @note In the default implementation the System Timer (Systick) is used as source of time base.
* The Systick configuration is based on HSI clock, as HSI is the clock
* used after a system Reset.
* Once done, time base tick starts incrementing: the tick variable counter is incremented
* each 1ms in the SysTick_Handler() interrupt handler.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
HAL_StatusTypeDef status = HAL_OK;
/* Configure Flash prefetch, Instruction cache */
/* Default configuration at reset is: */
/* - Prefetch disabled */
/* - Instruction cache enabled */
#if (INSTRUCTION_CACHE_ENABLE == 0U)
__HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
#endif /* INSTRUCTION_CACHE_ENABLE */
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif /* PREFETCH_ENABLE */
/* Use SysTick as time base source and configure 1ms tick (default clock after Reset is HSI) */
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
{
status = HAL_ERROR;
}
else
{
/* Init the low level hardware */
HAL_MspInit();
}
/* Return function status */
return status;
}
/**
* @brief This function de-Initializes common part of the HAL and stops the source of time base.
* @note This function is optional.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DeInit(void)
{
/* Reset of all peripherals */
__HAL_RCC_APB1_FORCE_RESET();
__HAL_RCC_APB1_RELEASE_RESET();
__HAL_RCC_APB2_FORCE_RESET();
__HAL_RCC_APB2_RELEASE_RESET();
__HAL_RCC_AHB_FORCE_RESET();
__HAL_RCC_AHB_RELEASE_RESET();
__HAL_RCC_IOP_FORCE_RESET();
__HAL_RCC_IOP_RELEASE_RESET();
/* De-Init the low level hardware */
HAL_MspDeInit();
/* Return function status */
return HAL_OK;
}
/**
* @brief Initialize the MSP.
* @retval None
*/
__weak void HAL_MspInit(void)
{
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes the MSP.
* @retval None
*/
__weak void HAL_MspDeInit(void)
{
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MspDeInit could be implemented in the user file
*/
}
/**
* @brief This function configures the source of the time base:
* The time source is configured to have 1ms time base with a dedicated
* Tick interrupt priority.
* @note This function is called automatically at the beginning of program after
* reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
* @note In the default implementation, SysTick timer is the source of time base.
* It is used to generate interrupts at regular time intervals.
* Care must be taken if HAL_Delay() is called from a peripheral ISR process,
* The SysTick interrupt must have higher priority (numerically lower)
* than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
* The function is declared as __weak to be overwritten in case of other
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
HAL_StatusTypeDef status = HAL_OK;
if ((uint32_t)uwTickFreq != 0UL)
{
/*Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) == 0U)
{
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
uwTickPrio = TickPriority;
}
else
{
status = HAL_ERROR;
}
}
else
{
status = HAL_ERROR;
}
}
else
{
status = HAL_ERROR;
}
/* Return function status */
return status;
}
/**
* @}
*/
/** @addtogroup HAL_Exported_Functions_Group2
* @brief HAL Control functions
*
@verbatim
===============================================================================
##### HAL Control functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Provide a tick value in millisecond
(+) Provide a blocking delay in millisecond
(+) Suspend the time base source interrupt
(+) Resume the time base source interrupt
(+) Get the HAL API driver version
(+) Get the device identifier
(+) Get the device revision identifier
@endverbatim
* @{
*/
/**
* @brief This function is called to increment a global variable "uwTick"
* used as application time base.
* @note In the default implementation, this variable is incremented each 1ms
* in SysTick ISR.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
uwTick += (uint32_t)uwTickFreq;
}
/**
* @brief Provides a tick value in millisecond.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
return uwTick;
}
/**
* @brief This function returns a tick priority.
* @retval tick priority
*/
uint32_t HAL_GetTickPrio(void)
{
return uwTickPrio;
}
/**
* @brief Set new tick Freq.
* @retval status
*/
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
{
HAL_StatusTypeDef status = HAL_OK;
assert_param(IS_TICKFREQ(Freq));
if (uwTickFreq != Freq)
{
/* Apply the new tick Freq */
status = HAL_InitTick(uwTickPrio);
if (status == HAL_OK)
{
uwTickFreq = Freq;
}
}
return status;
}
/**
* @brief return tick frequency.
* @retval Tick frequency.
* Value of @ref HAL_TickFreqTypeDef.
*/
HAL_TickFreqTypeDef HAL_GetTickFreq(void)
{
return uwTickFreq;
}
/**
* @brief This function provides minimum delay (in milliseconds) based
* on variable incremented.
* @note In the default implementation , SysTick timer is the source of time base.
* It is used to generate interrupts at regular time intervals where uwTick
* is incremented.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
uint32_t tickstart = HAL_GetTick();
uint32_t wait = Delay;
/* Add a freq to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
{
wait += (uint32_t)(uwTickFreq);
}
while ((HAL_GetTick() - tickstart) < wait)
{
}
}
/**
* @brief Suspend Tick increment.
* @note In the default implementation , SysTick timer is the source of time base. It is
* used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
* is called, the SysTick interrupt will be disabled and so Tick increment
* is suspended.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_SuspendTick(void)
{
/* Disable SysTick Interrupt */
CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
}
/**
* @brief Resume Tick increment.
* @note In the default implementation , SysTick timer is the source of time base. It is
* used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
* is called, the SysTick interrupt will be enabled and so Tick increment
* is resumed.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_ResumeTick(void)
{
/* Enable SysTick Interrupt */
SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
}
/**
* @brief Returns the HAL revision
* @retval version : 0xXYZR (8bits for each decimal, R for RC)
*/
uint32_t HAL_GetHalVersion(void)
{
return __STM32C0xx_HAL_VERSION;
}
/**
* @brief Returns the device revision identifier.
* @retval Device revision identifier
*/
uint32_t HAL_GetREVID(void)
{
return ((DBG->IDCODE & DBG_IDCODE_REV_ID) >> 16U);
}
/**
* @brief Returns the device identifier.
* @retval Device identifier
*/
uint32_t HAL_GetDEVID(void)
{
return ((DBG->IDCODE) & DBG_IDCODE_DEV_ID);
}
/**
* @brief Returns first word of the unique device identifier (UID based on 96 bits)
* @retval Device identifier
*/
uint32_t HAL_GetUIDw0(void)
{
return (READ_REG(*((uint32_t *)UID_BASE)));
}
/**
* @brief Returns second word of the unique device identifier (UID based on 96 bits)
* @retval Device identifier
*/
uint32_t HAL_GetUIDw1(void)
{
return (READ_REG(*((uint32_t *)(UID_BASE + 4U))));
}
/**
* @brief Returns third word of the unique device identifier (UID based on 96 bits)
* @retval Device identifier
*/
uint32_t HAL_GetUIDw2(void)
{
return (READ_REG(*((uint32_t *)(UID_BASE + 8U))));
}
/**
* @}
*/
/** @addtogroup HAL_Exported_Functions_Group3
* @brief HAL Debug functions
*
@verbatim
===============================================================================
##### HAL Debug functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Enable/Disable Debug module during STOP mode
(+) Enable/Disable Debug module during STANDBY mode
@endverbatim
* @{
*/
/**
* @brief Enable the Debug Module during STOP mode
* @retval None
*/
void HAL_DBGMCU_EnableDBGStopMode(void)
{
SET_BIT(DBG->CR, DBG_CR_DBG_STOP);
}
/**
* @brief Disable the Debug Module during STOP mode
* @retval None
*/
void HAL_DBGMCU_DisableDBGStopMode(void)
{
CLEAR_BIT(DBG->CR, DBG_CR_DBG_STOP);
}
/**
* @brief Enable the Debug Module during STANDBY mode
* @retval None
*/
void HAL_DBGMCU_EnableDBGStandbyMode(void)
{
SET_BIT(DBG->CR, DBG_CR_DBG_STANDBY);
}
/**
* @brief Disable the Debug Module during STANDBY mode
* @retval None
*/
void HAL_DBGMCU_DisableDBGStandbyMode(void)
{
CLEAR_BIT(DBG->CR, DBG_CR_DBG_STANDBY);
}
/**
* @}
*/
/** @addtogroup HAL_Exported_Functions_Group4
* @brief SYSCFG configuration functions
*
@verbatim
===============================================================================
##### HAL SYSCFG configuration functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Enable/Disable Pin remap
(+) Enable/Disable the I/O analog switch voltage booster
@endverbatim
* @{
*/
/**
* @brief Enable the I/O analog switch voltage booster
* @retval None
*/
void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void)
{
SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
}
/**
* @brief Disable the I/O analog switch voltage booster
* @retval None
*/
void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void)
{
CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
}
/**
* @brief Enable the remap on PA11_PA12
* @param PinRemap specifies which pins have to be remapped
* This parameter can be any combination of the following values:
* @arg @ref SYSCFG_REMAP_PA11
* @arg @ref SYSCFG_REMAP_PA12
* @retval None
*/
void HAL_SYSCFG_EnableRemap(uint32_t PinRemap)
{
/* Check the parameter */
assert_param(IS_HAL_REMAP_PIN(PinRemap));
SET_BIT(SYSCFG->CFGR1, PinRemap);
}
/**
* @brief Disable the remap on PA11_PA12
* @param PinRemap specifies which pins will behave normally
* This parameter can be any combination of the following values:
* @arg @ref SYSCFG_REMAP_PA11
* @arg @ref SYSCFG_REMAP_PA12
* @retval None
*/
void HAL_SYSCFG_DisableRemap(uint32_t PinRemap)
{
/* Check the parameter */
assert_param(IS_HAL_REMAP_PIN(PinRemap));
CLEAR_BIT(SYSCFG->CFGR1, PinRemap);
}
/**
* @brief Set Pin Binding
* @param pin_binding specifies which pin will bind a specific GPIO
* for each die package
* This parameter can be a value of @ref HAL_BIND_CFG
* @retval None
*/
void HAL_SYSCFG_SetPinBinding(uint32_t pin_binding)
{
/* Check the parameter */
assert_param(IS_HAL_SYSCFG_PINBINDING(pin_binding));
LL_SYSCFG_ConfigPinMux(pin_binding);
}
/**
* @brief return Pin Binding configuration
* @param pin_binding_source
* This parameter can be a value of @ref HAL_BIND_SCOURCE
* @retval PinMux configuration
*/
uint32_t HAL_SYSCFG_GetPinBinding(uint32_t pin_binding_source)
{
return LL_SYSCFG_GetConfigPinMux(pin_binding_source);
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

1
misc/gpu/stm32c0xx_hal.h Normal file
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#include "stm32c0xx_hal_def.h"

393
misc/gpu/stm32c0xx_hal_conf.h Normal file
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// TBD?
/**
******************************************************************************
* @file stm32c0116_discovery.h
* @author MCD Application Team
* @brief This file contains definitions for STM32C0116_DK's LEDs,
* push-buttons hardware resources (MB1684).
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32C0116_DK_H
#define STM32C0116_DK_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*
#include "stm32c0116_discovery_conf.h"
#include "stm32c0116_discovery_errno.h"
*/
#if (USE_BSP_COM_FEATURE > 0)
#if (USE_COM_LOG > 0)
#ifndef __GNUC__
#include "stdio.h"
#endif
#endif
#endif
/** @defgroup BSP BSP
* @{
*/
/** @defgroup STM32C0116_DK STM32C0116 DK
* @{
*/
/** @defgroup STM32C0116_DK_LOW_LEVEL LOW LEVEL
* @{
*/
/** @defgroup STM32C0116_DK_LOW_LEVEL_Exported_Types LOW LEVEL Exported Types
* @{
*/
typedef enum
{
LED3 = 0U,
LED_GREEN = LED3,
LEDn
} Led_TypeDef;
typedef enum
{
BUTTON_USER = 0U,
BUTTONn
} Button_TypeDef;
typedef enum
{
BUTTON_MODE_GPIO = 0U,
BUTTON_MODE_EXTI = 1U
} ButtonMode_TypeDef;
#if (USE_BSP_JOY_FEATURE > 0)
typedef enum
{
JOY_MODE_GPIO = 0U,
JOY_MODE_EXTI = 1U
}JOYMode_TypeDef;
typedef enum
{
JOY1 = 0U,
JOYn
}JOY_TypeDef;
typedef enum
{
JOY_NONE = 0x00U,
JOY_SEL = 0x01U,
JOY_DOWN = 0x02U,
JOY_LEFT = 0x04U,
JOY_RIGHT = 0x08U,
JOY_UP = 0x10U,
JOY_ALL = 0x1FU
}JOYPin_TypeDef;
#endif /* USE_BSP_JOY_FEATURE */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
typedef struct
{
void (* pMspInitCb)(ADC_HandleTypeDef *);
void (* pMspDeInitCb)(ADC_HandleTypeDef *);
}BSP_JOY_Cb_t;
#endif /* (USE_HAL_ADC_REGISTER_CALLBACKS == 1) */
#if (USE_BSP_COM_FEATURE > 0)
typedef enum
{
COM1 = 0U,
COMn
} COM_TypeDef;
typedef enum
{
COM_STOPBITS_1 = UART_STOPBITS_1,
} COM_StopBitsTypeDef;
typedef enum
{
COM_PARITY_NONE = UART_PARITY_NONE,
COM_PARITY_EVEN = UART_PARITY_EVEN,
COM_PARITY_ODD = UART_PARITY_ODD,
} COM_ParityTypeDef;
typedef enum
{
COM_HWCONTROL_NONE = UART_HWCONTROL_NONE,
COM_HWCONTROL_RTS = UART_HWCONTROL_RTS,
COM_HWCONTROL_CTS = UART_HWCONTROL_CTS,
COM_HWCONTROL_RTS_CTS = UART_HWCONTROL_RTS_CTS,
} COM_HwFlowCtlTypeDef;
typedef enum
{
COM_WORDLENGTH_7B = UART_WORDLENGTH_7B,
COM_WORDLENGTH_8B = UART_WORDLENGTH_8B,
COM_WORDLENGTH_9B = UART_WORDLENGTH_9B,
} COM_WordLengthTypeDef;
typedef struct
{
uint32_t BaudRate;
COM_WordLengthTypeDef WordLength;
COM_StopBitsTypeDef StopBits;
COM_ParityTypeDef Parity;
COM_HwFlowCtlTypeDef HwFlowCtl;
} COM_InitTypeDef;
#define MX_UART_InitTypeDef COM_InitTypeDef
#endif /* (USE_BSP_COM_FEATURE > 0) */
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
typedef struct
{
void (* pMspInitCb)(UART_HandleTypeDef *);
void (* pMspDeInitCb)(UART_HandleTypeDef *);
} BSP_COM_Cb_t;
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS == 1) */
/**
* @}
*/
/** @defgroup STM32C0116_DK_LOW_LEVEL_Exported_Constants LOW LEVEL Exported Constants
* @{
*/
/**
* @brief Define for STM32C0116_DK board
*/
#if !defined (USE_STM32C0116_DK)
#define USE_STM32C0116_DK
#endif /* USE_STM32C0116_DK */
/**
* @brief STM32C0116_DK BSP Driver version number V1.0.0
*/
#define STM32C0116_DK_BSP_VERSION_MAIN (uint32_t)(0x01) /*!< [31:24] main version */
#define STM32C0116_DK_BSP_VERSION_SUB1 (uint32_t)(0x00) /*!< [23:16] sub1 version */
#define STM32C0116_DK_BSP_VERSION_SUB2 (uint32_t)(0x00) /*!< [15:8] sub2 version */
#define STM32C0116_DK_BSP_VERSION_RC (uint32_t)(0x00) /*!< [7:0] release candidate */
#define STM32C0116_DK_BSP_VERSION ((STM32C0116_DK_BSP_VERSION_MAIN << 24)\
|(STM32C0116_DK_BSP_VERSION_SUB1 << 16)\
|(STM32C0116_DK_BSP_VERSION_SUB2 << 8 )\
|(STM32C0116_DK_BSP_VERSION_RC))
#define STM32C0116_DK_BSP_BOARD_NAME "STM32C0116-DK";
#define STM32C0116_DK_BSP_BOARD_ID "MB1684A";
/** @defgroup STM32C0116_DK_LOW_LEVEL_LED LOW LEVEL LED
* @{
*/
#define LED3_GPIO_PORT GPIOB
#define LED3_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()
#define LED3_GPIO_CLK_DISABLE() __HAL_RCC_GPIOB_CLK_DISABLE()
#define LED3_PIN GPIO_PIN_6
/**
* @}
*/
/** @defgroup STM32C0116_DK_LOW_LEVEL_BUTTON LOW LEVEL BUTTON
* @{
*/
/* Button state */
#define BUTTON_RELEASED 0U
#define BUTTON_PRESSED 1U
/**
* @brief User push-button
*/
#define BUTTON_USER_PIN GPIO_PIN_8
#define BUTTON_USER_GPIO_PORT GPIOA
#define BUTTON_USER_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define BUTTON_USER_GPIO_CLK_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE()
#define BUTTON_USER_EXTI_IRQn EXTI4_15_IRQn
#define BUTTON_USER_EXTI_LINE GPIO_PIN_8
/**
* @}
*/
/** @defgroup STM32C0116_DK_LOW_LEVEL_COM LOW LEVEL COM
* @{
*/
#if (USE_BSP_COM_FEATURE > 0)
/**
* @brief Definition for COM port1, connected to USART2
*/
#define COM1_UART USART2
#define COM1_CLK_ENABLE() __HAL_RCC_USART2_CLK_ENABLE()
#define COM1_CLK_DISABLE() __HAL_RCC_USART2_CLK_DISABLE()
#define COM1_TX_PIN GPIO_PIN_2
#define COM1_TX_GPIO_PORT GPIOA
#define COM1_TX_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define COM1_TX_GPIO_CLK_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE()
#define COM1_TX_AF GPIO_AF1_USART2
#define COM1_RX_PIN GPIO_PIN_3
#define COM1_RX_GPIO_PORT GPIOA
#define COM1_RX_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define COM1_RX_GPIO_CLK_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE()
#define COM1_RX_AF GPIO_AF1_USART2
#define COM_POLL_TIMEOUT 1000U
#endif /* (USE_BSP_COM_FEATURE > 0) */
/**
* @}
*/
/** @defgroup STM32C0116_DK_LOW_LEVEL_JOYSTICK LOW LEVEL JOYSTICK
* @{
*/
/* Joystick Pins definition */
#define JOY_KEY_NUMBER 5U
#define JOY1_SEL_PIN GPIO_PIN_8
#define JOY1_SEL_GPIO_PORT GPIOA
#define JOY1_SEL_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define JOY1_SEL_GPIO_CLK_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE()
#define JOY1_SEL_EXTI_IRQn EXTI4_15_IRQn
#define JOY1_SEL_EXTI_LINE GPIO_PIN_8
#define JOY1_DOWN_PIN GPIO_PIN_8
#define JOY1_DOWN_GPIO_PORT GPIOA
#define JOY1_DOWN_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define JOY1_DOWN_GPIO_CLK_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE()
#define JOY1_DOWN_EXTI_IRQn EXTI4_15_IRQn
#define JOY1_DOWN_EXTI_LINE GPIO_PIN_8
#define JOY1_LEFT_PIN GPIO_PIN_8
#define JOY1_LEFT_GPIO_PORT GPIOA
#define JOY1_LEFT_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define JOY1_LEFT_GPIO_CLK_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE()
#define JOY1_LEFT_EXTI_IRQn EXTI4_15_IRQn
#define JOY1_LEFT_EXTI_LINE GPIO_PIN_8
#define JOY1_RIGHT_PIN GPIO_PIN_8
#define JOY1_RIGHT_GPIO_PORT GPIOA
#define JOY1_RIGHT_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define JOY1_RIGHT_GPIO_CLK_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE()
#define JOY1_RIGHT_EXTI_IRQn EXTI4_15_IRQn
#define JOY1_RIGHT_EXTI_LINE GPIO_PIN_8
#define JOY1_UP_PIN GPIO_PIN_8
#define JOY1_UP_GPIO_PORT GPIOA
#define JOY1_UP_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define JOY1_UP_GPIO_CLK_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE()
#define JOY1_UP_EXTI_IRQn EXTI4_15_IRQn
#define JOY1_UP_EXTI_LINE GPIO_PIN_8
/**
* @brief Definition for Joystick, connected to ADC1
*/
#define JOY1_ADC ADC1
#define JOY1_CLK_ENABLE() __HAL_RCC_ADC_CLK_ENABLE()
#define JOY1_CLK_DISABLE() __HAL_RCC_ADC_CLK_DISABLE()
#define JOY1_CHANNEL_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define JOY1_FORCE_RESET() __HAL_RCC_ADC_FORCE_RESET()
#define JOY1_RELEASE_RESET() __HAL_RCC_ADC_RELEASE_RESET()
/* Definition for ADCx Channel Pin */
#define JOY1_CHANNEL_GPIO_PIN GPIO_PIN_8
#define JOY1_CHANNEL_GPIO_PORT GPIOA
/* Definition for ADCx's Channel */
#define JOY1_ADC_CHANNEL ADC_CHANNEL_8
#define JOY1_SAMPLING_TIME ADC_SAMPLETIME_39CYCLES_5
#define JOY1_PRESCALER ADC_CLOCK_SYNC_PCLK_DIV4
#define JOY_ADC_POLL_TIMEOUT 10U
/**
* @}
*/
/**
* @}
*/
/** @addtogroup STM32C0116_DK_LOW_LEVEL_Exported_Variables
* @{
*/
extern EXTI_HandleTypeDef hpb_exti[];
#if (USE_BSP_COM_FEATURE > 0)
extern UART_HandleTypeDef hcom_uart[];
extern USART_TypeDef *COM_UART[];
#endif /* USE_BSP_COM_FEATURE */
/**
* @}
*/
/** @addtogroup STM32C0116_DK_LOW_LEVEL_Exported_Functions
* @{
*/
int32_t BSP_GetVersion(void);
const uint8_t *BSP_GetBoardName(void);
const uint8_t *BSP_GetBoardID(void);
int32_t BSP_LED_Init(Led_TypeDef Led);
int32_t BSP_LED_DeInit(Led_TypeDef Led);
int32_t BSP_LED_On(Led_TypeDef Led);
int32_t BSP_LED_Off(Led_TypeDef Led);
int32_t BSP_LED_Toggle(Led_TypeDef Led);
int32_t BSP_LED_GetState(Led_TypeDef Led);
int32_t BSP_PB_Init(Button_TypeDef Button, ButtonMode_TypeDef ButtonMode);
int32_t BSP_PB_DeInit(Button_TypeDef Button);
int32_t BSP_PB_GetState(Button_TypeDef Button);
void BSP_PB_Callback(Button_TypeDef Button);
void BSP_PB_IRQHandler(Button_TypeDef Button);
#if (USE_BSP_COM_FEATURE > 0)
int32_t BSP_COM_Init(COM_TypeDef COM, COM_InitTypeDef *COM_Init);
int32_t BSP_COM_DeInit(COM_TypeDef COM);
#if (USE_COM_LOG > 0)
int32_t BSP_COM_SelectLogPort(COM_TypeDef COM);
#endif /* USE_COM_LOG */
#if (USE_HAL_UART_REGISTER_CALLBACKS > 0)
int32_t BSP_COM_RegisterDefaultMspCallbacks(COM_TypeDef COM);
int32_t BSP_COM_RegisterMspCallbacks(COM_TypeDef COM, BSP_COM_Cb_t *Callback);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
HAL_StatusTypeDef MX_USART6_Init(UART_HandleTypeDef *huart, MX_UART_InitTypeDef *COM_Init);
#endif /* USE_BSP_COM_FEATURE */
#if (USE_BSP_JOY_FEATURE > 0)
int32_t BSP_JOY_Init(JOY_TypeDef JOY, JOYMode_TypeDef JoyMode, JOYPin_TypeDef JoyPins);
int32_t BSP_JOY_DeInit(JOY_TypeDef JOY, JOYPin_TypeDef JoyPins);
int32_t BSP_JOY_GetState(JOY_TypeDef JOY);
#endif /* USE_BSP_JOY_FEATURE */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32C0116_DK_H */

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/**
******************************************************************************
* @file system_stm32c0xx.c
* @author MCD Application Team
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File
*
* This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32c0xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32c0xx_system
* @{
*/
/** @addtogroup STM32C0xx_System_Private_Includes
* @{
*/
#include "stm32c0xx.h"
#if !defined (HSE_VALUE)
#define HSE_VALUE (48000000UL) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE (48000000UL) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
#if !defined (LSI_VALUE)
#define LSI_VALUE (32000UL) /*!< Value of LSI in Hz*/
#endif /* LSI_VALUE */
#if !defined (LSE_VALUE)
#define LSE_VALUE (32768UL) /*!< Value of LSE in Hz*/
#endif /* LSE_VALUE */
/**
* @}
*/
/** @addtogroup STM32C0xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32C0xx_System_Private_Defines
* @{
*/
/************************* Miscellaneous Configuration ************************/
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
//#define VECT_TAB_SRAM
#define VECT_TAB_OFFSET 0x0U /*!< Vector Table base offset field.
This value must be a multiple of 0x100. */
/******************************************************************************/
/**
* @}
*/
/** @addtogroup STM32C0xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32C0xx_System_Private_Variables
* @{
*/
/* The SystemCoreClock variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t SystemCoreClock = 48000000UL;
const uint32_t AHBPrescTable[16UL] = {0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL, 6UL, 7UL, 8UL, 9UL};
const uint32_t APBPrescTable[8UL] = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
/**
* @}
*/
/** @addtogroup STM32C0xx_System_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32C0xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system.
* @param None
* @retval None
*/
void SystemInit(void)
{
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) / HSI division factor
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
*
* - If SYSCLK source is LSI, SystemCoreClock will contain the LSI_VALUE
*
* - If SYSCLK source is LSE, SystemCoreClock will contain the LSE_VALUE
*
* (**) HSI_VALUE is a constant defined in stm32c0xx_hal_conf.h file (default value
* 48 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (***) HSE_VALUE is a constant defined in stm32c0xx_hal_conf.h file (default value
* 48 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
*
* @param None
* @retval None
*/
void SystemCoreClockUpdate(void)
{
uint32_t tmp;
uint32_t hsidiv;
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
{
case RCC_CFGR_SWS_0: /* HSE used as system clock */
SystemCoreClock = HSE_VALUE;
break;
case (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0): /* LSI used as system clock */
SystemCoreClock = LSI_VALUE;
break;
case RCC_CFGR_SWS_2: /* LSE used as system clock */
SystemCoreClock = LSE_VALUE;
break;
case 0x00000000U: /* HSI used as system clock */
default: /* HSI used as system clock */
hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV))>> RCC_CR_HSIDIV_Pos));
SystemCoreClock = (HSI_VALUE/hsidiv);
break;
}
/* Compute HCLK clock frequency --------------------------------------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
/* HCLK clock frequency */
SystemCoreClock >>= tmp;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

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// (c) Copyright 2023 by Coinkite Inc. This file is covered by license found in COPYING-CC.
//
// Version string. Careful with changes because parsed by python code and probably others.
//
#include "version.h"
// the Makefile will define BUILD and GIT values.
const char version_string[] = RELEASE_VERSION
#ifdef BUILD_TIME
" time=" BUILD_TIME
#endif
#ifdef GIT_HASH
" git=" GIT_HASH
#endif
#ifndef RELEASE
" DEV=1"
#endif
;

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misc/gpu/version.h Normal file
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/*
* (c) Copyright 2023 by Coinkite Inc. This file is covered by license found in COPYING-CC.
*/
#pragma once
#include <stdint.h>
// Public version number for humans. Lots more version data added by Makefile.
#define RELEASE_VERSION "1.0.0"
extern const char version_string[];